Datasheet INT200PFI2, INT200PFI1, INT200TFI2, INT200TFI1 Datasheet (POWER)

Page 1
INT200
HSD2
HS IN
PI–284C–072291
COM
8
5
7
6
N/C
LS IN
LS OUT
1
4
2
3
V
DD
HSD1
Low-side Driver IC
Low-side Drive and High-side Control with Simultaneous Conduction Lockout
Product Highlights
®
5 V CMOS Compatible Control Inputs
• Combines logic inputs for low and high-side drives
Built-in High-voltage Level Shifters
• Integrated level shifters simplify high-side interface
• Can withstand up to 800 V for direct interface to the INT201 high-side driver
• Pulsed high-voltage level shifters reduce power consumption
Gate Drive Output for an External MOSFET
• Provides 300 mA sink/150 mA source current
• Can drive MOSFET gate at up to 15 V
• External MOSFET allows flexibility in design for various motor sizes
Built-in Protection Features
• Simultaneous conduction lockout protection
• UV lockout
Description
The INT200 Low-side driver IC provides gate drive for an external low-side MOSFET switch and high-side level shifting. When used in conjunction with the INT201 high-side driver, the INT200 provides a simple, cost-effective interface between low-voltage control logic and high-voltage loads. The INT200 is designed to be used with rectified 110 V or 220 V supplies. Both high-side and low-side switches can be controlled independently from ground-referenced 5 V logic inputs on the low side driver.
HV
INT201
V
DD
HS IN
LS IN
Figure 1. Typical Application
Figure 2. Pin Configuration.
INT200
3-PHASE
BRUSHLESS
DC MOTOR
PI-11762-012396
Built-in protection logic prevents both switches from turning on at the same time and shorting the high voltage supply. Pulsed level shifting saves power and provides enhanced noise immunity. The circuit is powered from a nominal 15 V supply to provide adequate gate drive for external N-channel MOSFETs.
Applications include motor drives, electronic ballasts, and uninterruptible power supplies. The INT200 can also be used to implement full- bridge and multi-phase configurations.
The INT200 is available in 8-pin plastic DIP and SOIC packages.
ORDERING INFORMATION
PART PACKAGE ISOLATION
NUMBER OUTLINE VOLTAGE
INT200PFI1 P08A 600 V INT200TFI1 T08A 600 V INT200PFI2 P08A 800 V INT200TFI2 T08A 800 V
January 1996
Page 2
INT200
Pin Functional Description
Pin 1:
Active-low logic-level input HS IN controls the pulse circuit which signals the INT201 high-side driver.
Pin 2:
Active-high logic level input LS IN controls the low side driver output.
Pin 3: LS OUT is the driver output which
controls the low-side MOSFET.
Pin 4: COM connection; analog reference point
for the circuit.
Pin 5:
Level shift output HSD 2 signals the high-side driver to turn off. One short, precise pulse is sent on each positive transition of
HS IN
.
Pin 6:
Level shift output HSD 1 signals the high-side driver to turn on. Two short, precise pulses are sent on each negative transition of
HS IN
.
Pin 7:
N/C for creepage distance.
Pin 8: V
supplies power to the logic, high-
DD
side interface, and low-side driver.
V
DD
LINEAR
REGULATOR
UV
LOCKOUT
HS IN
LS IN
COM
Figure 3. Functional Block Diagram of the INT200
PULSE
CIRCUIT
DELAY
HSD1 HSD2
LS OUT
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INT200 Functional Description
INT200
5 V Regulator
The 5 V linear regulator circuit provides the supply voltage for the control logic and high-voltage level shift circuit. This allows the logic section to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply.
Undervoltage Lockout
The undervoltage lockout circuit disables the LS OUT pin and both HSD pins whenever the VDD power supply falls below typically 9.0 V, and maintains this condition until the VDD power supply rises above typically 9.35 V. This guarantees that both MOSFETs will remain off during power-up or fault conditions.
HSD1/HSD2
The HSD1 and HSD2 outputs are connected to integrated high-voltage N­channel MOSFET transistors which perform the level-shifting function for communication to the high-side driver. Controlled current capability allows the drain voltage to float with the high-side driver. Two individual channels produce a true differential communication channel for accurately controlling the high-side driver in the presence of fast moving high-voltage waveforms.
Pulse Circuit
The pulse circuit provides the two high­voltage level shifters with precise timing signals. Two pulses are sent over HSD1 to signal the high-side driver to turn on. One pulse is sent over HSD2 to signal the high-side driver to turn off. The combination of differential communication with the precise timing provides maximum immunity to noise.
Conduction Latch
An RS latch prevents the low-side driver and high-side driver from being on at the same time, regardless of the input signals. .
Delay Circuit
The delay circuit matches the low-side propagation delay with the combination of the pulse circuit, high voltage level shift, and high-side driver propagation delays. This ensures that the low-side driver and high-side driver will never be on at the same time during switching transitions in either direction.
Driver
The CMOS drive circuit provides drive power to the gate of the MOSFET used on the low side of the half bridge circuit. The driver consists of a CMOS buffer capable of driving an external transistor gate at up to 15 V.
HV+
8765
C2
INT201
1234
8765
INT200
1234
R1
V
DD
HS IN
D1
C1
LS IN
HV-
Figure 4. Using the INT200 and INT201 in a 3-phase Configuration.
R2
Q2
PHASE 1
Q1
PHASE 2
PHASE 3
3-PHASE
BRUSHLESS
DC MOTOR
PI-1461-042695
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INT200
General Circuit Operation
One phase of a three-phase brushless DC motor drive circuit is shown in Figure 4 to illustrate an application of the INT200/201. The LS IN signal directly controls MOSFET Q1. The
HS IN
signal causes the INT200 to command the INT201 to turn MOSFET Q2 on or off as required. The INT200 will ignore input signals that would command both Q1 and Q2 to conduct simultaneously, protecting against shorting the HV+ bus to HV-.
Local bypassing for the low-side driver is provided by C1. Bootstrap bias for the high-side driver is provided by D1 and C2. Slew rate and effects of parasitic oscillations in the load waveforms are controlled by resistors R1 and R2.
The inputs are designed to be compatible with 5 V CMOS logic levels and should not be connected to VDD. Normal CMOS power supply sequencing should be observed. The order of signal application
should be VDD, logic signals, and then HV+. V
should be supplied from a
DD
low impedance voltage source.
Maximum frequency of operation is limited by power dissipation due to high­voltage switching, gate charge, and bias
power. Figure 5 indicates the maximum The length of time that the high-side can remain on is limited by the size of the bootstrap capacitor. Applications with extremely long high-side on times
switching frequency as a function of
input voltage and gate charge. For higher
ambient temperatures, the switching
frequency should be derated linearly. require special techniques discussed in AN-10.
400
PDIP
VIN = 200 V
300
200
100
Switching Frequncy (kHz)
0
0 100 200
VIN = 300 V VIN = 400 V
Gate Charge (nC)
PI-1782-020696
Figure 5. Switching Frequency versus Gate Charge for a) PDIP and b) SOIC.
400
VIN = 200 V
300
200
100
Switching Frequncy (kHz)
0
0 100 200
VIN = 300 V VIN = 400 V
Gate Charge (nC)
SOIC
PI-1785-020696
HV+
8765
INT201
1234
V
DD
8765
INT200
HV-
OSCILLATOR
Figure 6. Using the INT200 and INT201 to Drive a Fluorescent Lamp.
1234
FLUORESCENT
LAMP
PI-1462-042695
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INT200
ABSOLUTE MAXIMUM RATINGS
HSD1/HSD2 Voltage (1 Suffix) .................................600 V
(2 Suffix) .................................800 V
HSD1/HSD2 Slew Rate ........................................... 10 V/ns
VDD Voltage ................................................................ 16.5 V
Logic Input Voltage ...................................... -0.3V to 5.5 V
LS OUT Voltage ................................-0.3 V to VDD + 0.3 V
Storage Temperature ....................................... –65 to 125°C
Ambient Temperature ........................................ -40 to 85°C
Junction Temperature................................................. 150°C
Lead Temperature
(2)
.................................................... 260°C
Conditions
Parameter Symbol
(Unless Otherwise Specified) Min Typ Max Units
VDD = 15 V, COM = 0V
TA = -40 to 85°C
LOGIC
1
Power Dissipation
PF Suffix (TA = 25°C) ......................................... 1.25 W
(TA = 70°C) ....................................... 800 mW
TF Suffix (TA = 25°C) ......................................... 1.04 W
(TA = 70°C) ....................................... 667 mW
Thermal Impedance (θJA)
PF Suffix ........................................................... 100°C/W
TF Suffix........................................................... 120°C/W
1. Unless noted, all voltages referenced to COM, TA = 25°C
2. 1/16" from case for 5 seconds.
Input Current, High or Low
Input Voltage High
Input Voltage Low
Input Voltage Hysteresis
HSD OUTPUTS
Breakdown Voltage
Off-State Output Current
On-State Output Current
On-State Pulse Width
I
IH, IIL
V
IH
V
IL
V
HY
BV
DSS
I
HSD(OFF)
I
HSD(ON)
t
HSD(ON)
V
V
HSD1
HSD1
VIH = 4.0 V VIL = 1.0 V
1 Suffix 2 Suffix
, V
= 500 V
HSD2
, V
= 10 V
HSD2
0 10 150
-20 0 20
4.0
1.0
0.3 0.7
600 700 800 900
0.1 15
525
156
µA
V
V
V
V
µA
mA
ns
Output Capacitance
V
, V
C
OSS
HSD1
HSD2
= 25 V
10
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INT200
Parameter Symbol
LS OUT
Conditions
(Unless Otherwise Specified) Min Typ Max Units
VDD = 15 V, COM = 0V
TA = -40 to 85°C
Output Voltage High
Output Voltage Low
Output Short Circuit Current
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
SYSTEM RESPONSE
Deadtime (Low Off to High On)
V
V
t
t
Dt
OH
OL
I
OS
d(on)
t
d(off)
t
Io= -20 mA
Io= 40 mA
Vo= 0V
See Note 1
See Figure 7
r
f
P+
See Figure 7
See Figure 7
See Figure 7
See Figure 8
Vo= V
DD
VDD-1.0 VDD-0.5
0.3 1.0
-150
300
0.6 1.0
80 120
0.5 1
50 100
0 450
V
V
mA
µs
ns
µs
ns
ns
Deadtime (High Off to Low On)
Dt
P-
UNDERVOLTAGE LOCKOUT
Input UV Trip-off Voltage
V
DD(UV)
Input UV Hysteresis
SUPPLY
Supply Current
Supply Voltage
F
6
1/96
V
I
DD
DD
See Figure 8
See Figure 2
0 300
8.5 9.0 10
175 350
1.5 3.0
10 16
ns
V
mV
mA
V
Page 7
INT200
NOTES:
1. Applying a short circuit to the LS OUT pin for more than 500 µs will exceed the thermal rating of the package, resulting in destruction of the part.
2. VDD supply must have less than 30 output impedance.
15 V
5 V
INPUT
CL
1000 pF
1
2
3
4
INT200
8
1 µF 0.1 µF
7
6
5
INPUT
15 V
LS OUT
0 V
0 V
t
d(off)
90%
10%
50%
50%
t
d(on)
t
t
r
f
90%
10%
Figure 7. Switching Time Test Circuit.
8765
1234
15 V
8765
47 µF
35 V
0.1 µF
1234
INT201
INT200
1000 pF
1000 pF
INPUT
LS OUT
HS OUT
5 V
0 V
15 V
0 V
15 V
0 V
PI-1463-042695
50%
Dt
p+
50%
50%
50%
Dt
p-
Figure 8. Dead Time Test Circuit.
PI-1465-042695
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Page 8
INT200
BREAKDOWN vs. TEMPERATURE
1.1
1.0
(Normalized to 25°C)
Breakdown Voltage (V)
0.9
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
PI-176B-051391
PACKAGE POWER DERATING
1.5
PF Suffix
1.0
TF Suffix
0.5
Power Dissipation (W)
0
0 25 50 75 100 125 150
Junction Temperature (°C)
PI-1763-013196
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Page 9
INT200
P08A Plastic DIP-8
Dim. inches mm  A .395 MAX 10.03 MAX B .090-.110 2.29-2.79 C .015-.021 0.38-0.53
D .040 TYP 1.02 TYP E .015-.030 0.38-0.76 F .125 MIN 3.18 MIN G .015 MIN 0.38 MIN H .125-.135 3.18-3.43
J .300-.320 7.62-8.13 K .245-.255 6.22-6.48 L .009-.015 0.23-0.38 
Notes:
1. Package dimensions conform to JEDEC specification MS-001-AB for standard dual in­line (DIP) package .300 inch row spacing (PLASTIC) 8 leads (issue B, 7/85).
2. Controlling dimensions: inches.
3. Dimensions are for the molded body and do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .010 inch (.25 mm) on any side.
4. These dimensions measured with the leads constrained to be perpendicular to package bottom.
5. Pin 1 orientation identified by end notch or dot adjacent to Pin 1.
Note 5
G
E
58
A
(3)
D
41
J
(4)
K
(3)
H
F
°
C
B
L
0 – 15
PI-1842-050196
T08A Plastic SO-8
DIM
G 
Notes:
1. Package dimensions conform to JEDEC specification MS-012-AA for standard small outline (SO) package, 8 leads, 3.75 mm (.150 inch) body width (issue A, June 1985).
2. Controlling dimensions are in mm.
3. Dimensions are for the molded body and do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .15 mm (.006 inch) on any side.
4. Pin 1 side identified edge by chamfer on top of the package body or indent on Pin 1 end.  
 A B C D E F
H J K
inches
0.189-0.197
0.050 TYP 
0.014-0.019
0.012 TYP
0.053-0.069
0.004-0.010
0.228-0.244
0.007-0.010
0.021-0.045
0.150-0.157
mm
4.80-5.00
1.27 TYP
0.35-0.49
0.31 TYP
1.35-1.75
0.10-0.25
5.80-6.20
0.19-0.25
0.51-1.14
3.80-4.00
85
(3)
K
1
(3)
A
D 
C
4
G
E
H
B
F
J
0-8˚ TYP.
PI-1845-050196
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Page 10
INT200
Notes
10
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Page 11
Notes
INT200
1/96
F
11
Page 12
INT200
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others.
PI Logo and
TOPSwitch
are registered trademarks of Power Integrations, Inc.
©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086
WORLD HEADQUARTERS
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