Page 1
TECHNICAL DATA
Hex Inverter
The IN74LV04 is a low-voltage Si-gate CMOS device that is pin
and function compatible with 74HC/HCT04A.
The IN74LV04 provides six inverting buffers.
• Wide Operating Voltage: 1.0÷5.5 V
• Optimized for Low Voltage applications: 1.0÷3.6 V
• Accepts TTL input levels between V
• Low Input Current
LOGIC DIAGRAM
=2.7 V and VCC =3.6 V
CC
IN74LV04
ORDERING INFORMATION
IN74LV04N Plastic
IN74LV04D SOIC
IZ74LV04 Chip
TA = -40° ÷ 125° C for all packages
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Input Output
A Y
L H
H L
1
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IN74LV04
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
VCC DC supply voltage (Referenced to GND)
IIK*1 DC input diode current
IOK*2 DC output diode current
Io*3 DC output source or sink current
-0.5 ÷ +7.0
±20
±50
±25
V
mA
mA
mA
-bus driver outputs
I
DC GND current for types with
GND
±50
mA
- bus driver outputs
ICC DC VCC current for types with
±50
mA
- bus driver outputs
PD Power dissipation per package, plastic DIP+
SOIC package+
Tstg Storage temperature
TL Lead temperature, 1.5 mm from Case for 10 seconds
750
mW
500
-65 ÷ +150 °C
260
°C
(Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
1
*
: V
2
*
: Vo < -0.5V or Vo > VCC+0.5V
3
*
: -0.5V < Vo < VCC+0.5V
SOIC Package: : - 8 mW/°C from 70° to 125°C
< -0.5V or V
I
I
> V
+0.5V
CC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 1.0 5.5 V
VIN, V
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused outputs must be left open.
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -40 +125
tr, tf Input Rise and Fall Time VCC =1.2 V
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
V
CC
0
0
0
0
1000
700
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
°C
ns
CC
).
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
,
Symbol Parameter Test Conditions
CC
V
25°C -40°C ÷
min max
min max min max
85°C
IN74LV04
-40°C ÷
125°C
Unit
VIH High-Level Input
Voltage
VIL Low-Level Input
Voltage
VOH High-Level
Output Voltage
VOL Low-Level Output
Voltage
V
IIL Low-Level Input
Leakage Current
IIН High-Level Input
Leakage Current
IСС Quiescent Supply
Current
(per Package)
* : VCC= (3.3±0.3) V
1.2
1.2
VI = VIL
I
= -50 µA
O
= VIL
V
I
I
= -6.0 µA
O
VI = VIH
I
= 50 µA
O
= VIH or VIL
I
= 6.0 mА
I
O
2.0
3.0
3.6
2.0
3.0
3.6
1.2
2.0
*
0.9
1.4
2.1
2.5
1.1
1.92
2.92
-
0.9
-
1.4
-
2.1
-
2.5
-
0.3
-
0.6
-
0.9
-
1.1
-
1.0
-
1.9
-
2.9
-
0.9
-
1.4
-
2.1
-
2.5
-
0.3
-
0.6
-
0.9
-
1.1
-
1.0
-
1.9
-
2.9
-
-
-
-
-
0.3
-
0.6
-
0.9
-
1.1
-
-
-
* 2.48 - 2.34 - 2.20 - V
1.2
2.0
-
0.09
-
0.09
-
0.09
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
3.0 - 0.33 - 0.4 - 0.5 V
- -0.1 - -1.0 - -1.0
VI = VCC * - 0.1 - 1.0 - 1.0
= 0 В or V
V
I
* - 2.0 - 20 - 40
CC
IO = 0 µA
V
V
V
V
µA
µA
µA
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IN74LV04
AC ELECTRICAL CHARACTERISTICS (C
V
CC
Symbol Parameter
V
=50 pF, tLH = tHL = 6.0 ns, VIL=0V, VIH=V
L
25°C -40°C ÷ 85°C -40°C ÷ 125°C
min max
t
(t
THL,
t
(t
PHL,
CI Input Capacitance 3.0
Output Transition
TLH)
Time, Any Output
(Figure 1)
Propagation Delay,
PLH)
Input A to Output Y
(Figure 1)
1.2
2.0
*
1.2
2.0
*
-
-
-
-
-
-
70
16
10
90
23
14
- - 3.5 - 3.5 pF
CPD Power Dissipation Capacitance (Per
Inverter)
Used to determine the no-load dynamic power consumption:
= CPDV
P
D
∑(C
LVCC
2
fI+ ∑(CLV
CC
2
fo) – sum of the outputs
2
fo), fI - input frequency, fo - output frequency (MHz)
CC
Input А
0.1
t
HL
0.9
V
1
t
PHL
0.9
Guaranteed Limit
min max min max
-
-
-
-
-
-
t
LH
V
1
0.1
t
PLH
85
20
13
120
28
18
-
-
-
-
-
-
ТА=25°С, VI=0V÷VCC
42
V
CC
GND
100
150
24
15
34
21
CC, RL
Unit
ns
pF
=1 kΩ)
PULSE
GENERATOR
Output Y
V
I
V = 0.5 V
1 CC
DEVICE
UNDER
R
T
0.9
V
V
1
t
THL
0.1 0.1
1
t
Figure 1. Switching Waveforms
V
CC
V
O
TEST
Figure 2. Test Circuit
TLH
0.9
V
CC
GND
Termination resistance RT – should
be equal to Z
C
L
R
L
of pulse generators
OUT
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CHIP PAD DIAGRAM IZ74LV04
IN74LV04
12
13
Chip marking
25LV04
(x=0.127; y=0.580)
14
01
02
Pad size 0.108 x 0.108 mm (Pad size is given as per
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No Symbol X Y
01 А1 0.111 0.228
02 Y1 0.333 0.111
03 A2 0.600 0.111
04 Y2 0.770 0.111
05 A3 1.006 0.111
06 Y3 1.138 0.293
07 GND 1.138 0.477
08 Y4 1.138 0.786
09 A4 1.006 0.970
10 Y5 0.771 0.970
11 A5 0.600 0.970
12 Y6 0.332 0.970
13 A6 0.111 0.855
14 Vcc 0.111 0.619
10
11
04
03
±
1.35 0.03
metallization
09
08
±
07
1.20 0.03
06
05
layer)
5
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