Page 1
Hex Inverted Buffers with
Open-Collector Outputs
This device contains hex inverted buffers with open-collector. It
performs the Boolean function Y=A in positive Logic.
•
High Output Voltage (30 V)
•
High Speed ( t
•
Low Power Dissipation (P
= 8.5 ns typical)
PD
D
= 18 mW per Gate)
TECHNICAL DATA
IN74LS06
ORDERING INFORMATION
IN74LS06N Plastic
IN74LS06D SOIC
TA = 0° to 70° C for all
packages
LOGIC DIAGRAM
1
A1
3
A2
5
A3
9
A4
11
A5
13
A6
PIN 14 =V
PIN 7 = GND
CC
2
4
6
8
10
12
Y1
Y2
Y3
Y4
Y5
Y6
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
AY
HL
LH
1
Page 2
IN74LS06
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
Supply Voltage 7.0 V
Input Voltage 5.5 V
IN
Output Voltage 30 V
Tstg Storage Temperature Range -65 to +150
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
V
IH
V
IL
V
OH
I
OL
T
A
Supply Voltage 4.75 5.25 V
High Level Input Voltage 2.0 V
Low Level Input Voltage 0.8 V
High Level Output Voltage 30 V
Low Level Output Current 40 mA
Ambient Temperature Range 0 +70
°
C
°
C
DC ELECTRICAL CHARACTERISTICS
over full operating conditions
Guaranteed Limit
Symbol Parameter Test Conditions Min Max Unit
V
I
OH
V
OL
Input Clamp Voltage VCC = min, IIN = -18 mA -1.5 V
IK
High Level Output Current VCC = min, VOH= max 250
Low Level Output Voltage VCC = min, IOL = 16 mA 0.4 V
VCC = min, IOL = 40 mA 0.7
I
IH
High Level Input Current VCC = max, VIN = 2.7 V 20
VCC = max, VIN = 5.5 V 1 mA
I
IL
I
CC
Low Level Input Current VCC = max, VIN = 0.4 V -0.2 mA
Supply Current VCC = max Total with
18 mA
outputs high
Total with
60
outputs low
µ
A
µ
A
2
Page 3
IN74LS06
AC ELECTRICAL CHARACTERISTICS
= 110 Ω, tr = 15 ns, tf = 6.0 ns)
R
L
(TA = 25°C, VCC = 5.0 V, CL = 15 pF,
Symbol Parameter Min Max Unit
t
t
PLH
PHL
Propagation Delay, Input A to Output Y 15 ns
Propagation Delay, Input A to Output Y 20 ns
Figure 1. Switching Waveforms
NOTE A. CL includes probe and jig capacitance.
Figure 2. Test Circuit
3
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