Page 1
TECHNICAL DATA
Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The IN74HCT74A is identical in pinout to the LS/ALS74. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
This device consists of two D flip-flops with individual Set, Reset,
and Clock inputs. Information at a D-input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip-flop. The Set
and Reset inputs are asynchronous.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA
IN74HCT74A
ORDERING INFORMATION
IN74HCT74AN Plastic
IN74HCT74AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =V
PIN 7 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
LH X XHL
HL X XLH
LL X XH*H
HH HHL
HH LLH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care
*
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IN74HCT74A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond whitch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) 0 500 ns
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
CC
V
°
C
CC
).
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IN74HCT74A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Leve l
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
IL
20 µA
IL
4.0 mA
IL
20 µA
IL
4.0 mA
VIN=VCC or GND 5.5
Leakage Current
I
CC
Maximum Quiescent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
CC
Additional Quiescent
∆
I
Supply Current
VIN=2.4 V, Any One Input
V
IN=VCC
or GND, Other
Inputs
I
=0µA
OUT
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
-55°C
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5 0.26 0.33 0.4
±
0.1
±
1.0
±
5.5 1.0 10 40
≥
-55°C25°C to
125°C
5.5 2.9 2.4
125
°
C
1.0
Unit
V
V
V
V
µ
A
µ
A
mA
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IN74HCT74A
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
t
t
t
TLH
PLH
PLH
f
max
, t
, t
, t
C
IN
C
PD
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 4)
Maximum Propagati on Delay, Clock to Q or Q
PHL
(Figures 1 and 4)
Maximum Propagation Delay, Set or Reset to Q or
PHL
Q (Figures 2 and 4)
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per Enabled
Output)
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
(VCC =5.0 V±10%,CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C
≤85°
C≤125°C
to
-55°C
30 24 20 MHz
24 30 36 ns
24 30 36 ns
15 19 22 ns
Typical @25°C,V
=5.0 V
CC
130 pF
Unit
TIMING REQUIREMENTS
Symbol Parameter
t
t
t
t
tr, t
su
t
h
rec
w
w
Minimum Setup Time, Data to Clock
(Figure 3)
Minimum Hold Time, Clock to Data
(Figure 3)
Minimum Recovery Time, Set or
Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure
1)
Minimum Pul se Width, Set or Re set
(Figure 2)
Maximum Input Rise and Fall Times
f
(Figure 1)
(VCC =5.0 V±10%,CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C to-55°C
≤85°
C
15 19 22 ns
333ns
689ns
15 19 22 ns
15 19 22 ns
500 500 500 ns
≤
125°C
Unit
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IN74HCT74A
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
88
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