Page 1
TECHNICAL DATA
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The IN74HCT574A is identical in pinout to the LS/ALS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip-flops, but when Output Enable is high, all device
outputs are forced to the high-impedance state; thus, data may be
stored even when the outputs are not enabled.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA
IN74HCT574A
ORDERING INFORMATION
IN74HCT574AN Plastic
IN74HCT574ADW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=V
PIN 10 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output
Enable
LHH
LLL
LL,H, X no
HXXZ
X = don’t care
Z = high impedance
Clock D Q
change
418
Page 2
IN74HCT574A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
35
±
75
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) 0 500 ns
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
CC
V
°
C
CC
).
419
Page 3
IN74HCT574A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN= VIL or V
≤
I
OUT
VIN= VIL or V
≤
I
OUT
IL
20 µA
IL
6.0 mA
IH
20 µA
IH
6.0 mA
VIN=VCC or GND 5.5
Leakage Current
I
OZ
I
CC
Maximum Three
State Leakage
Current
Maximum Qui escent
Supply Current
Output in High-Impedance
State
V
=VIH or V
IN
V
= VCC or GND
OUT
IL
VIN=VCC or GND
=0µA
I
OUT
(per Package)
CC
Additional Quiescent
∆
I
Supply Current
VIN=2.4 V, Any One Input
V
IN=VCC
or GND,
Other Inputs
I
=0µA
OUT
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5 0.26 0.33 0.4
5.5
±
±
0.1
0.5
±
±
1.0
5.0
±
±
5.5 4.0 40 160
≥
-55°C25°C to
125°C
5.5 2.9 2.4
C
1.0
10
Unit
V
V
V
V
µ
A
µ
A
µ
A
mA
420
Page 4
IN74HCT574A
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
t
t
t
t
TLH
PLH
PLZ
PZH
f
max
, t
, t
, t
, t
C
IN
C
OUT
C
PD
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 4)
Maximum Propagati on Delay, Clock to Q
PHL
(Figures 1 and 4)
Maximum Propagation Delay, Output Enable to Q
PHZ
(Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
PZL
(Figures 2 and 5)
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
Maximum Input Capacitance 10 10 10 pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Flip-Flop)
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C
≤85°
≤
C
125°C
Unit
to
-55°C
30 24 20 MHz
30 38 45 ns
28 35 42 ns
28 35 42 ns
12 15 18 ns
15 15 15 pF
Typical @25°C,V
=5.0 V
CC
58 pF
TIMING REQUIREMENTS
Symbol Parameter
t
SU
t
h
t
w
t
r, tf
Minimum Set up Time, Data to
Clock (Figure 3)
Minimum Hold T ime, Clock
to Data (Figure 3)
Minimum Pulse W idth , Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C to
≤85°
C
≤
125°C
-55°C
10 13 15 ns
555ns
15 19 22 ns
500 500 500 ns
Unit
421
Page 5
IN74HCT574A
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
422
Loading...