
TECHNICAL DATA
Octal 3-State Noninverting Buffer/Line
Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The IN74HCT241A is identical in pinout to the LS/ALS241. The
IN74HCT241 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers, and
other bus-oriented systems. The de vice has noninverting outputs and
two output enables. Enable A is active-low and Enable B is activehigh.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA
IN74HCT241A
ORDERING INFORMATION
IN74HCT241AN Plastic
IN74HCT241ADW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=V
PIN 10 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output Inputs Output
EnableAAYAEnableBBYB
LLL HLL
LHH HHH
HXZ LXZ
X = don’t care
Z = high impedance
286

IN74HCT241A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
35
±
75
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) 0 500 ns
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
CC
CC
V
°
C
).
287

IN74HCT241A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
Minimum High-
IH
Level Input
V
= VCC-0.1 V
OUT
≤
I
OUT
20 µA
Voltage
V
Maximum Low -
IL
Level Input
V
I
OUT
OUT
= 0.1 V
≤
20 µA
Voltage
V
OH
Minimum HighLevel Output
VIN= V
≤
I
OUT
IH
20 µA
Voltage
VIN= V
IH
≤
I
6.0 mA
OUT
V
OL
Maximum LowLevel Output
VIN = V
≤
I
OUT
IL
20 µA
Voltage
VIN= V
IL
≤
I
6.0 mA
OUT
I
IN
Maximum Input
VIN=VCC or GND 5.5
Leakage Current
I
OZ
I
CC
Maximum three
State Leakage
Current
Maximum
Quiescent Supply
Output in High-Impedance State
V
= VIL or V
IN
V
OUT=VCC
V
IN=VCC
=0µA
I
OUT
IH
or GND
or GND
Current
(per Package)
CC
Additional
∆
I
Quiescent
Supply Current
NOTE: Total Supply Current = I
VIN = 2.4 V, Any One Input
CC
V
I
OUT
+ ∑∆I
or GND, Other Inputs
IN=VCC
=0µA
CC
V
CC
Guaranteed Limit
25 °C
≤
85
to
°
C
≤
125
°
-55°C
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5 0.26 0.33 0.4
5.5
±
±
0.1
0.5
±
±
±
1.0
5.0±10.0
5.5 4.0 40 160
≥
-55°C25°C to
125°C
5.5 2.9 2.4
C
1.0
Unit
V
V
V
V
µ
A
µ
A
µ
A
mA
288

IN74HCT241A
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
t
t
t
t
TLH
PLH
PLZ
PZH
, t
, t
, t
, t
C
IN
C
OUT
C
PD
Maximum Propagation Delay, A to YA or B to
PHL
YB (Figures 1 and 3)
Maximum Propagation Delay, Output Enable to
PHZ
YA or YB (Figures 2 and 4)
Maximum Propagation Delay, Output Enable to
PZL
YA or YB (Figures 2 and 4)
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 3)
Maximum Input Capacitance 10 10 10 pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enable
Output)
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C
≤85°
C≤125°C
Unit
to
-55°C
23 29 35 ns
30 38 45 ns
26 33 39 ns
12 15 18 ns
15 15 15 pF
Typical @25°C,V
=5.0 V
CC
55 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
289

IN74HCT241A
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
290