Page 1
TECHNICAL DATA
39
Quad 2-Input AND Gate
High-Performance Silicon-Gate CMOS
The IN74HCT08A may be used as a level converter for intertacing
TTL or NMOS outputs to high-speed CMOS inputs.
The IN74HCT08A is identical in pinout to the LS/ALS08.
•
TTL/NMOS-Compatible Input Levels.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA
IN74HCT08A
ORDERING INFORMATION
IN74HCT08AN Plastic
IN74HCT08AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =V
CC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
AB Y
LL L
LH L
HL L
HH H
Page 2
IN74HCT08A
40
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
OUT
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
I
IN
DC Input Current, per Pin
±
20
mA
I
OUT
DC Output Current, per Pin
±
25
mA
I
CC
DC Supply Current, VCC and GND Pins
±
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types -55 +125
°
C
tr, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Page 3
IN74HCT08A
41
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
25 °C
to
-55°C
≤
85
°
C
≤
125
°
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low Level Input Voltage
V
OUT
=0.1 V
I
OUT
≤
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High-Level
Output Voltage
VIN=V
IH
I
OUT
≤
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN=V
IH
I
OUT
≤
4.0 mA
4.5 3.98 3.84 3.7
V
OL
Maximum Low-Level
Output Voltage
VIN=VIH or V
IL
I
OUT
≤
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or V
IL
I
OUT
≤
4.0 mA
4.5 0.26 0.33 0.4
I
IN
Maximum Inp ut
Leakage Current
VIN=VCC or GND 5.5
±
0.1
±
1.0
±
1.0
µ
A
I
CC
Maximum Quiescen t
Supply Current
(per Package)
VIN=VCC or GND
I
OUT
=0µA
5.5 1.0 10 40
µ
A
∆
I
CC
Additional Quiescent
Supply Current
VIN = 2.4 V, Any One Input
V
IN=VCC
or GND, Other
Inputs
≥
-55°C25°C to
125°C
mA
I
OUT
=0µA
5.5 2.9 2.4
Page 4
IN74HCT08A
42
AC ELECTRICAL CHARACTERISTICS
(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limits
Symbol Parameter
25 °C to
-55°C
≤85°
C
≤
125°C
Unit
t
PLH
, t
PHL
Maximum Propagat i on Delay, Input
A or B to Output Y
(Figures 1 and 2)
19 24 28 ns
t
TLH
, t
THL
Maximum Output Transition Time,
Any Output (Figures 1 and 2)
15 19 22 ns
C
IN
Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per
Gate)
Typical @25°C,V
CC
=5.0 V
C
PD
Used to determine the no-load
dynamic power consumptio n:
P
D=CPDVCC
2
f+ICCV
CC
20 pF
Figure 1. Switching Waveforms. Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
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