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Quad 2-Input NOR Gate
High-Performance Silicon-Gate CMOS
The IN74HCT02A is identical in pinout to the LS/ALS02. The
IN74HCT02A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA
TECHNICAL DATA
IN74HCT02A
ORDERING INFORMATION
IN74HCT02AN Plastic
IN74HCT02AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =V
PIN 7 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
AB Y
LL H
LH L
HL L
HH L
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IN74HCT02A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) 0 500 ns
IN
or V
OUT
)≤VCC.
and V
IN
should be constrained to the range
OUT
CC
V
°
C
CC
).
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IN74HCT02A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN= V
IL
≤
I
20 µA
OUT
VIN= V
IL
≤
OUT
OUT
OUT
≤
20 µA
≤
4.0 mA
4.0 mA
IL
IL
I
VIN=VIH or V
I
VIN=VIH or V
I
VIN=VCC or GND 5.5
Leakage Current
I
CC
Maximum Qui escent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
CC
Additional Quiescent
∆
I
Supply Current
VIN = 2.4 V, Any One Input
V
IN=VCC
or GND, Other
Inputs
I
=0µA
OUT
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
-55°C
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5 0.26 0.33 0.4
±
0.1
±
1.0
±
5.5 1.0 10 40
≥
-55°C25°C to
125°C
5.5 2.9 2.4
125
°
C
1.0
Unit
V
V
V
V
µ
A
µ
A
mA
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IN74HCT02A
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
t
t
TLH
PLH
, t
, t
C
IN
C
PD
Maximum Propagation Delay, Input A or B to
PHL
Output Y (Figures 1 and 2)
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 2)
Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per Gate)
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
25 °C
≤85°
C≤125°C
Unit
to
-55°C
16 20 24 ns
15 19 22 ns
Typical @25°C,V
=5.0 V
CC
25 pF
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Figure 1. Switching Waveforms Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
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