Page 1
TECHNICAL DATA
89
Dual 2-Bit Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74HC75 is identical in pinout to the LS/ALS75. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 2-bit transparent latches
and can be used as temporary storage for binary information between
processing units and input/output or indicator units. Each latch stores
the input data while Latch Enable is at a logic low. The outputs follow
the data inputs when Latch Enable is at a logic high.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC75
ORDERING INFORMATION
IN74HC75N Plastic
IN74HC75D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
D Latch
Enable
QQ
LHLH
HHHL
X L Q0 Q0
X = Don’t Care
Q0 = latched data
LOGIC DIAGRAM
PIN 5=V
CC
PIN 12 = GND
PIN ASSIGNMENT
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IN74HC75
90
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
OUT
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
I
IN
DC Input Current, per Pin
±
20
mA
I
OUT
DC Output Current, per Pin
±
25
mA
I
CC
DC Supply Current, VCC and GND Pins
±
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types -55 +125
°
C
tr, t
f
Input Rise and Fall Time (Figure 1) VCC =2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
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IN74HC75
91
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
25 °C
to
-55°C
≤
85
°
C
≤
125
°
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low Level Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High-Level
Output Voltage
VIN=VIH or V
IL
I
OUT
≤
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
VIN= VIL or V
IH
I
OUT
≤
20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or V
IH
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
VIN=VCC or GND 6.0
±
0.1
±
1.0
±
1.0
µ
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
I
OUT
=0µA
6.0 4.0 40 80
µ
A
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IN74HC75
92
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C
to
-55°C
≤85°
C≤125°C
Unit
t
PLH
, t
PHL
Maximum Propagat i on Delay, D to Q (Figures 1
and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLH
, t
PHL
Maximum Propagation Delay , D to Q
(Figures 1 and 5)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
PLH
, t
PHL
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay ,Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Latch)
Typical @25°C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
35 pF
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C to
-55°C
≤85°
C
≤
125°C
Unit
t
SU
Minimum Set up Time,
Input D to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time,Latch
Enable to D (Figure 4)
2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
ns
t
w
Minimum Pulse Width , Latch
Enable Input
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r, tf
Maximum Input Ri se and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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IN74HC75
93
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
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