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Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The IN74HC74A is identical in pinout to the LS/ALS74. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset,
and Clock inputs. Information at a D-input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip-flop. The Set
and Reset inputs are asynchronous.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
TECHNICAL DATA
IN74HC74A
ORDERING INFORMATION
IN74HC74AN Plastic
IN74HC74AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =V
PIN 7 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
LH X XHL
HL X XLH
LL X XH*H
HH HHL
HH LLH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go hi gh
simultaneously.
X = don’t care
*
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IN74HC74A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
V
IN
=4.5 V
CC
=6.0 V
CC
and V
should be constrained to the range
OUT
0
0
0
CC
1000
500
400
V
°
C
ns
CC
).
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IN74HC74A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
CC
Maximum Quiescent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
6.0 2.0 20 80
125
°
C
1.0
Unit
V
V
V
V
µ
A
µ
A
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IN74HC74A
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 4)
t
PLH
, t
Maximum Propagati on Delay, Clock to Q or Q
PHL
(Figures 1 and 4)
t
PLH
, t
Maximum Propagation Delay, Set or Reset to Q
PHL
or Q (Figures 2 and 4)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
C
IN
Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Flip-Flop)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
V
CC
25 °C
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6.0
30
35
100
20
17
105
21
18
75
15
13
Typical @25°C,V
Guaranteed Limit
≤85°
4.8
24
28
125
25
21
130
26
22
95
19
16
C
=5.0 V
CC
≤
125°C
4.0
20
24
150
30
26
160
32
27
110
22
19
39 pF
Unit
MHz
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
su
Minimum Set up Time, Data to Cl ock
(Figure 3)
t
h
Minimum Hold Time, C lock to Data
(Figure 3)
t
rec
Minimum Rec overy Time, Se t or
Reset Inactive to Clock (Figure 2)
t
w
t
w
Minimum Pulse Width, Clock (Figure1)2.0
Minimum Pulse Width , Set or Reset
(Figure 2)
tr, t
Maximum Input Ri se and Fall Times
f
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
CC
Guaranteed Limit
25 °C to-55°C
80
16
14
3.0
3.0
3.0
8.0
8.0
8.0
60
12
10
60
12
10
1000
500
400
≤85°
100
20
17
3.0
3.0
3.0
8.0
8.0
8.0
75
15
13
75
15
13
1000
500
400
≤
C
125°C
120
Unit
ns
24
20
3.0
ns
3.0
3.0
8.0
ns
8.0
8.0
90
ns
18
15
90
ns
18
15
1000
ns
500
400
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IN74HC74A
Figure 1. Switching Waveform Figure 2. Switching Waveform
Figure 3. Switching Waveform Figure 4.Test Circuit
EXPANDED LOGIC DIAGRAM
83
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