Page 1
TECHNICAL DATA
465
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Performance Silicon-Gate CMOS
The IN74HC652 is identical in pinout to the LS/ALS652. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data
directly from the data bus or from the internal storage registers.
Direction and Output Enable are provided to select the read-time or
stored data function. Data on the A or B Data bus, or both, can be
stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of
the select or enable or enable control pins. When A-to-B Source and
B-to-A Source are in the real-time transfer mode, it is also possible to
store data without using the internal D-type flip-flops by simultaneously enabling Direction and Output Enable. In this configuration
each output reinforces its input. Thus, when all other data sources to
the two sets of bus lines are at high impedance, each set of bus lines
will remain at its last state.
The IN74HC652 has noninverted outputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC652
ORDERING INFORMATION
IN74HC651N Plastic
IN74HC651DW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
CC
PIN 12 = GND
Page 2
IN74HC652
466
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
OUT
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
I
IN
DC Input Current, per Pin
±
20
mA
I
OUT
DC Output Current, per Pin
±
35
mA
I
CC
DC Supply Current, VCC and GND Pins
±
75
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types -55 +125
°
C
tr, t
f
Input Rise and Fall Time (Figures2,3) VCC =2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
Page 3
IN74HC652
467
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
25 °C
to
-55°C
≤
85
°
C
≤
125
°
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low Level Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High-Level
Output Voltage
VIN=VIH or V
IL
I
OUT
≤
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or V
IL
I
OUT
≤
6.0 mA
I
OUT
≤
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
VIN= VIL or V
IH
I
OUT
≤
20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or V
IL
I
OUT
≤
6.0 mA
I
OUT
≤
7.8 mA)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
VIN=VCC or GND
(Pins 1,2,3,21,22,and 23)
6.0
±
0.1
±
1.0
±
1.0
µ
A
I
OZ
Maximum ThreeState Leakage
Current
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT=VCC
or GND,
I/O Pins
6.0
±
0.5
±
5.0
±
10
µ
A
I
CC
Maximum Qui escent
Supply Current
(per Package)
VIN=VCC or GND
I
OUT
=0µA
6.0 8 .0 80 160
µ
A
Page 4
IN74HC652
468
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C
to
-55°C
≤85°C≤
125°C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input A to Output
B (or Input B to Output A)
(Figures 2,3 and 9)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
PLH
, t
PHL
Maximum Propagation Delay, A-to-B Clock to
Output B (or B-to-A Clock to Output A)
(Figures 1 and 9)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
t
PLH
, t
PHL
Maximum Propagation Delay, A-to-B Source to
Output B (or B-to-A Source to Output A) (Figures
4 and 9)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , Direction or
Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Direction or
Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
Maximum Input Capacitance - 10 10 10 pF
C
OUT
Maximum Three-State I/O Capacitance
(Output in High-Impedance State
-151515pF
Power Dissipation Capacitance (Per Channel)
Typical @25°C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
60 pF
Page 5
IN74HC652
469
TIMING REQUIREMENTS
(Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C to-55°C
≤85°
C
≤
125°C
Unit
t
su
Minimum Setup Time, Input A to
A-to-B Clock (or Input B to B-to-A
Clock) (Figure 7)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold T ime, A-to-B Clock
to Input A (or B-to-A Clock to
Input B) (Figure 7)
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
t
w
Minimum Pulse W idth, A-to-B C lock
(or B-to-A Clock)
(Figure 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, t
f
Maximum Input Rise and Fa ll T imes
(Figures 2 and 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
TIMING DIAGRAM
Page 6
IN74HC652
470
FUNCTION TABLE
Dir. OE CAB CBA SAB SBA A B FUNCTION
INPUTS INPUTS Both the A bus and the B bus are inputs.
L H X X X X Z Z The output functions of the A and B bus
are disabled.
X X INPUTS INPUTS Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS INPUTS The A bus are outputs and the B bus are
inputs.
X
*
XXL L
H
L
H
The data at the B bus are displayed at the
A bus.
LLX
*
XL L
H
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
X
*
X X H Qn X The data stored to the internal flip-flops,
are displayed at the A bus.
X
*
XH H
L
H
L
The data at the B bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus are
outputs.
XX*LX L
H
L
H
The data at the A bus are displayed at the
B bus.
HH X*LX L
H
L
H
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
XX*H X X Qn T he da ta sto r ed to the internal flip-flops
are displayed at the B bus.
X
*
HX L
H
L
H
The data at the A bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS OUTPUT S Both the A bus and the B bus are outputs
H L X X H H Qn Qn The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
H H Qn Qn The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH
TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY
LOW TO TRANSITION OF THE CLOCK INPUTS
Page 7
IN74HC652
471
SWITCHING DIAGRAMS
Figure 1. Switching Waveforms
Figure 2. A Data Port = Input, B Data Port =
Output
Figure 3. A Data Port = Output, B Data Port =
Input
Figure 4. Switching Waveforms Figure 5. Switching Waveforms
Page 8
IN74HC652
472
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
Figure 9. Test Circuit Figure 10. Test Circuit
Page 9
IN74HC652
473
EXPANDED LOGIC DIAGRAM
Loading...