Datasheet IN74HC651N, IN74HC651DW Datasheet (INTEGRAL)

TECHNICAL DATA

IN74HC651

Octal 3-State Bus Transceivers and D Flip-Flops

High-Performance Silicon-Gate CMOS

The IN74HC651 is identical in pinout to the LS/ALS651. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

These devices consists of bus transceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-to-A Source are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

The IN74HC651 has inverted outputs.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 2.0 to 6.0 V

•

Low Input Current: 1.0 µA

•

High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

IN74HC651N Plastic

IN74HC651DW SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 24=V

PIN 12 = GND

CC

456

IN74HC651

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

I

OUT

I

CC

P

DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+

±

20

±

35

±

75

750 500

Tstg Storage Temperature -65 to +150

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mA mA mA

mW

°

C

°

C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

T

A

tr, t

f

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

DC Supply Voltage (Referenced to GND) 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

OUT

Operating Temperature, All Package Types -55 +125 Input Rise and Fall Time (Figures 2,3) VCC =2.0 V

IN

or V

OUT

)≤VCC.

V

CC

V

CC

and V

IN

=4.5 V

=6.0 V

OUT

should be constrained to the range

0 0 0

CC

1000

500 400

°

ns

V

C

CC

).

457

IN74HC651

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

Symbol Parameter Test Conditions V

V

OH

V

OL

I

IN

I

OZ

Minimum High-Level

IH

Input Voltage

Maximum Low -

IL

Level Input Voltage

Minimum High-Level Output Voltage

Maximum Low-Level Output Voltage

Maximum Input Leakage Current

Maximum ThreeState Leakage Current

V

=0.1 V or VCC-0.1 V

OUT



≤

I

20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT



 ≤

I

20 µA

OUT

VIN=VIH or V



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

VIN= VIL or V



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

IL

20 µA

IL

6.0 mA

7.8 mA

IH

20 µA

IL

6.0 mA

7.8 mA)

VIN=VCC or GND (Pins 1,2,3,21,22,and 23)

Output in High-Impedance State V

= V

or V

IN

IL

IH

V

OUT=VCC

or GND,

I/O Pins

I

CC

Maximum Qui escent Supply Current

VIN=VCC or GND

=0µA

I

OUT

(per Package)

V

CC

Guaranteed Limit

25 °C

to

≤

85

°

C

≤

125

°

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.98

5.48

0.1

0.26

±

0.1

±

0.5

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.84

5.34

0.1

0.33

±

1.0

±

5.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.7

5.2

0.1

0.4

±

6.0 8 .0 80 160

C

1.0

10

Unit

V

µ

A

µ

A

µ

A

458

IN74HC651

AC ELECTRICAL CHARACTERISTICS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

t

PLH

, t

Maximum Propagation Delay, Input A to Output

PHL

B (or Input B to Output A) (Figures 2,3 and 9)

t

PLH

, t

Maximum Propagation Delay, A-to-B Clock to

PHL

Output B (or B-to-A Clock to Output A) (Figures 1 and 9)

t

PLH

, t

Maximum Propagation Delay, A-to-B Source to

PHL

Output B (or B-to-A Source to Output A) (Figures 4 and 9)

t

PLZ

, t

Maximum Propagation Delay , Direction or

PHZ

Output Enable to Output A or B (Figures 5,6 and 10)

t

PZL

, t

Maximum Propagation Delay , Direction or

PZH

Output Enable to Output A or B (Figures 5,6 and 10)

t

TLH

, t

Maximum Output Transition Time, Any Output

THL

(Figure 2)

C

IN

C

OUT

Maximum Input Capacitance - 10 10 10 pF Maximum Three-State I/O Capacitance

(Output in High-Impedance State

V

CC

Guaranteed Limit

25 °C

≤85°C≤

125°C

Unit

to

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

180

36 31

240

48 41

220

44 37

170

34 29

180

36 31

60 12 10

225

45 38

300

60 51

275

55 47

215

43 37

225

45 38

75 15 13

270

54 46

360

72 61

330

66 56

255

51 43

270

54 46

90 18 15

ns

-151515pF

Power Dissipation Capacitance (Per Channel)

C

PD

Used to determine the no-load dynamic power consumption: P

D=CPDVCC

2

f+ICCV

CC

Typical @25°C,V

60 pF

=5.0 V

CC

459

IN74HC651

TIMING REQUIREMENTS

(Input tr=tf=6.0 ns)

Symbol Parameter V

t

su

Minimum Setup Time, Input A to A-to-B Clock (or Input B to B-to-A Clock) (Figure 7)

t

h

Minimum Hold T ime, A-to-B Clock to Input A (or B-to-A Clock to Input B) (Figure 7)

t

w

Minimum Pulse W idth, A-to-B C lock (or B-to-A Clock) (Figure 7)

tr, t

Maximum Input Rise and Fa ll T imes

f

(Figures 2 and 3)

TIMING DIAGRAM

V

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

CC

Guaranteed Limit

25 °C to-55°C

50 10

9

25

5 5

75 15 13

1000

500 400

≤85°

65 13 11

30

6 5

95 19 16

1000

500 400

≤

C

125°C

75

Unit

ns 15 13

40

ns

8 7

110

ns 22 19

1000

ns

500 400

460

IN74HC651

FUNCTION TABLE

Dir. OE CAB CBA SAB SBA A B FUNCTION

INPUTS INPUTS Both the A bus and the B bus are inputs.

L H X X X X Z Z The output functions of the A and B bus

are disabled.

X X INPUTS INPUTS Both the A and B bus are used for inputs

to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs.

OUTPUTS INPUTS The A bus are outputs and the B bus are

inputs.

*

X

LLX

X

HH X*LX H

H L X X H H Qn Qn The data stored to the internal flip-flops

X : DON’T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS

*

: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY

LOW TO TRANSITION OF THE CLOCK INPUTS

XXL H

*

XL H

L

H L

H

The data at the B bus are displayed at the A bus.

The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse.

*

X X H Qn X The data stored to the internal flip-flops,

are displayed at the A bus.

*

XH L

H

H L

The data at the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus.

INPUTS OUTPUTS The A bus are inputs and the B bus are

outputs.

XX*LX H

L

L H

The data at the A bus are displayed at the B bus.

The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse.

XX*H X X Qn The data stored to the internal flip-flops

are displayed at the B bus.

*

X

HX H

L

L H

The data at the A bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus.

OUTPUTS OUTPUT S Both the A bus and the B bus are outputs

are displayed at the A and B bus respectively.

H H Qn Qn The output at the A bus are displayed at

the B bus, the output at the B bus are displayed at the A bus respec.

461

IN74HC651

SWITCHING DIAGRAMS

Figure 1. Switching Waveforms

Figure 2. A Data Port = Input, B Data Port =

Output

Figure 4. Switching Waveforms Figure 5. Switching Waveforms

Figure 3. A Data Port = Output, B Data Port =

Input

462

Figure 6. Switching Waveforms

IN74HC651

Figure 7. Switching Waveforms

Figure 9. Test Circuit Figure 10. Test Circuit

463

IN74HC651

EXPANDED LOGIC DIAGRAM

464