Page 1
TECHNICAL DATA
Octal 3-State Noninverting
Bus Transceiver
High-Performance Silicon-Gate CMOS
The IN74HC623 is identical in pinout to the LS/ALS623. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC623 is a 3-state noninverting transceiver that is used
for 2-way communication between data buses. Two separate enables
are available. The enable for bus A to B is active-high, the enable for
bus B to A is active-low.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC623
ORDERING INFORMATION
IN74HC623N Plastic
IN74HC623DW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=V
PIN 10 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
Output
Enable
L L Data Transmitted
L H Data Transmitted
H L Buses Isolated
L H (High Impedance
Direction Operation
from Bus B to
Bus A
from Bus A to
Bus B
State)
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IN74HC623
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
35
±
75
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
CC
V
CC
and V
IN
=4.5 V
=6.0 V
OUT
should be constrained to the range
0
0
0
CC
1000
500
400
°
ns
V
C
CC
).
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IN74HC623
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
I
OZ
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Maximum ThreeState Leakage
Current
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN= VIL or V
≤
I
OUT
VIN= VIL or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
6.0 mA
7.8 mA
IH
20 µA
IH
6.0 mA
7.8 mA
VIN=VCC or GND, Pin 1 or
19
Output in High-Impedance
State
V
= V
or V
IN
IL
IH
V
OUT=VCC
or GND,
I/O Pins
I
CC
Maximum Quiesce nt
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
Guaranteed Limit
CC
25 °C
to
≤
≤
85
°
125
°
C
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
±
0.5
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
±
5.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
±
6.0 8 .0 80 160
C
1.0
10
Unit
V
V
V
V
µ
A
µ
A
µ
A
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IN74HC623
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
PLH
, t
Maximum Propagation Delay, A to B , B to A
PHL
(Figures 1 and 3)
t
PLZ
, t
Maximum Propagation Delay , Direction or
PHZ
Output Enable to A or B (Figures 2 and 4)
t
PZL
, t
Maximum Propagation Delay , Direction or
PZH
Output Enable to A or B (Figures 2 and 4)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 3)
C
IN
C
OUT
Maximum Input Capacitance (Pin 1 or Pin 19) - 10 10 10 pF
Maximum Three-State I/O Capacitance
(I/O in High-Impedance State)
V
CC
Guaranteed Limit
25 °C
≤85°C≤
125°C
Unit
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
100
20
17
150
30
26
150
30
26
60
12
10
125
25
21
190
38
33
190
38
33
75
15
13
150
30
26
225
45
38
225
45
38
90
18
15
ns
ns
ns
ns
-151515pF
Power Dissipation Capacitance (Per Transceiver
Typical @25°C,V
Channel)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
40 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
=5.0 V
CC
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IN74HC623
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
450
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