Page 1
TECHNICAL DATA
Octal 3-State
Inverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The IN74HC534A is identical in pinout to the LS/ALS534. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup time is clocked, in inverted form, to the
outputs with the rising edge of the Clock. The Output Enable input
does not affect the states of the flip-flops, but when Output Enable is
high, the outputs are forced to the high impedance state. Thus, data
may be stored even when the outputs are not enabled.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC534A
ORDERING INFORMATION
IN74HC534AN Plastic
IN74HC534ADW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=V
PIN 10 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output
Enable
LHL
LLH
LL,H, X no
HXXZ
X = don’t care
Z = high impedance
Clock D Q
change
398
Page 2
IN74HC534A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
V
V
I
I
CC
IN
OUT
I
IN
OUT
CC
P
D
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
±
20
±
35
±
75
750
500
Tstg Storage Temperature -65 to +150
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
V
=4.5 V
CC
=6.0 V
CC
IN
and V
should be constrained to the range
OUT
0
0
0
CC
1000
500
400
V
°
C
ns
CC
).
399
Page 3
IN74HC534A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN= VIL or V
≤
I
OUT
VIN= VIL or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
6.0 mA
7.8 mA
IH
20 µA
IH
6.0 mA
7.8 mA
VIN=VCC or GND 6.0
Leakage Current
I
OZ
I
CC
Maximum Three
State Leakage
Current
Maximum Quiescent
Supply Current
Output in High-Impedance
State
V
=VIH or V
IN
V
= VCC or GND
OUT
IL
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
±
0.5
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
±
5.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
±
6.0 4.0 40 160
C
1.0
10
Unit
V
V
V
V
µ
A
µ
A
µ
A
400
Page 4
IN74HC534A
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 4)
t
PLH
, t
Maximum Propagati on Delay, Clock to Q
PHL
(Figures 1 and 4)
t
PLZ
, t
Maximum Propagation Delay, Output Enable to Q
PHZ
(Figures 2 and 5)
t
PZH
, t
Maximum Propagation Delay, Output Enable to Q
PZL
(Figures 2 and 5)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
C
IN
C
OUT
Maximum Input Capacitance - 10 10 10 pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
V
CC
Guaranteed Limit
25 °C
≤85°
C≤125°C
Unit
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6.0
30
35
125
25
21
150
30
26
150
30
26
75
15
13
5.0
24
28
155
31
26
190
38
33
190
38
33
95
19
16
4.0
20
24
190
38
32
225
45
38
225
45
38
110
22
19
MHz
ns
ns
ns
ns
-151515pF
Power Dissipation Capacitance (Per Flip-Flop)
C
PD
TIMING REQUIREMENTS
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
SU
Minimum Set up T ime, Data to
Clock (Figure 3)
t
h
Minimum Hold Time, Clock
to Data (Figure 3)
t
w
Minimum Pulse Width , Clock
(Figure 1)
t
r, tf
Maximum Input Rise an d Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
CC
25 °C to
-55°C
50
10
9
5
5
5
60
12
10
1000
500
400
Typical @25°C,V
34 pF
Guaranteed Limit
≤85°
C
65
13
11
5
5
5
75
15
13
1000
500
400
=5.0 V
CC
≤
125°C
75
15
13
90
18
15
1000
500
400
Unit
ns
5
ns
5
5
ns
ns
401
Page 5
IN74HC534A
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
402
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