Datasheet IN74HC4053N, IN74HC4053DW Datasheet (INTEGRAL)

Analog Multiplexer/Demultiplexer

High-Performance Silicon-Gate CMOS

The IN74HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from V

to VEE).

CC

The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off.

The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

•

Fast Switching and Propagation Speeds

•

Low Crosstalk Between Switches

•

Diode Protection on All Inputs/Outputs

•

Analog Power Supply Range (V

•

Digital (Control) Power Supply Range (V

•

Low Noise

CC-VEE

)=2.0 to 12.0 V

-GND)=2.0 to 6.0 V

CC

TECHNICAL DATA

IN74HC4053

ORDERING INFORMATION

IN74HC4053N Plastic

IN74HC4053DW SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

Triple Single-Pole, Double-Position

Plus Common Off

PIN 16 =V

PIN 7 = V

PIN 8 = GND

CC

EE

FUNCTION TABLE

Control Inputs ON

Enable Select Channels

CBA L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1 HXXX None

X = don’t care

507

IN74HC4053

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

EE

V V

I DC Input Current Into or Out of Any Pin

P

Tstg Storage Temperature -65 to +150

T

Positive DC Supply Voltage (Referenced to GND) (Referenced to V

)

EE

-0.5 to +7.0

-0.5 to +14.0 Negative DC Supply Voltage (Referenced to GND) -7.0 to +0.5 V Analog Input Voltage V

IS

Digital Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

IN

Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+

Lead Temperature, 1 mm from Case for 10 Seconds

L

- 0.5 to VCC+0.5

EE

±

25

750 500

260

V

mA

mW

°

C

°

C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

V

EE

V

IS

V

IN

*

V

IO

T

A

tr, t

f

*

For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn;

i. e., the current out of the switch may contain both V device will be unaffected unless the Maximum Ratings are exceeded.

Positive Supply Voltage (Referenced to GND) (Referenced to V

)

EE

2.0

6.0

12.0 Negative DC Supply Voltage (Referenced to GND) - 6.0 GND V Analog Input Voltage V

EE

Digital Input Voltage (Referenced to GND) GND V

V

CC

Static or Dynamic Voltage Across Switch - 1.2 V Operating Temperature, All Package Types -55 +125 Input Rise and Fall Time (Channel Select

or Enable Inputs)

VCC =2.0 V V

=4.5 V

CC

V

=6.0 V

CC

and switch input components. The reliability of the

CC

0 0 0

1000

500 400

°

ns

V

V V

C

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V

and V

IN

should be constrained to the range

OUT

indicated in the Recommended Operating Conditions..

Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or

V

). Unused Analog I/O pins may be left open or terminated.

CC

508

IN74HC4053

DC ELECTRICAL CHARACTERISTICS

V

=GND, Except Where Noted

EE

Digital Section (Voltages Referenced to GND)

Symbol Parameter Test Conditions V

V

Minimum High-Level

IH

R

= Per Spec 2.0

ON

Input Voltage, Channel-Select or Enable Inputs

V

Maximum Low -Level

IL

R

= Per Spec 2.0

ON

Input Voltage, Channel-Select or Enable Inputs

I

IN

Maximum Input Leakage Current,

V

IN=VCC

V

=-6.0 V

EE

or GND,

Channel-Select or Enable Inputs

I

CC

Maximum Quiescent Supply Current (per Package)

Channel Select = VCC or GND Enable = V V

= VCC or GND

IS

V

= 0 V VEE = GND

IO

V

or GND

CC

= -6.0

EE

V

4.5

6.0

4.5

6.0

CC

Guaranteed Limit

25 °C

to

≤

85

°

C

-55°C

1.5

3.15

4.2

0.3

0.9

1.2

±

0.1

2 8

1.5

3.15

4.2

0.3

0.9

1.2

±

1.0

20 80

≤

125

°

1.5

3.15

4.2

0.3

0.9

1.2

±

1.0

40

160

Unit

C

V

µ

A

µ

A

DC ELECTRICAL CHARACTERISTICS

Analog Section

V

CC

Symbol Parameter Test Conditions V V

R

ON

Maximum “ON” Resistanc e VIN=VIL or V

V

= VCC or V

IS

≤

2.0 mA(Figure 1)

I

S

VIN=VIL or V V

= VCC or V

IS

IH

EE

IH

EE

4.5

6.0

4.5

(Endpoints)

≤

2.0 mA(Figure 1)

I

S

∆

R

Maximum Difference in

ON

“ON” Resistance Between Any Two Channels in the

V V I

or V

IN=VIL

= 1/2 (VCC- VEE)

IS

≤

2.0 mA

S

IH

6.0

4.5

6.0

Same Package

I

OFF

ON

Maximum Off- Channel Leakage Current, Any One Channel

Maximum Off- Channel Leakage Current, Common Channel

Maximum On- Channel Leakage Current, Channel to Channel

VIN=VIL or V V

= VCC- V

IO

IH

EE

Switch Off (Figure 2) VIN=VIL or V

VIO= VCC- V

IH

EE

Switch Off (Figure 3) VIN=VIL or V

IH

Switch to Switch = V

- VEE (Figure 5)

CC

6.0 -6.0 0.1 0.5 1.0

6.0 -6.0 0.1 1.0 2.0

V

EE

0.0

-4.5

-6.0

0.0

-4.5

-6.0

0.0

-4.5

-6.0

Guaranteed Limit

25 °C

≤

85

to

°

C

-55°C 190

120 100

150 100

80 30

12 10

240 150 125

190 125

100

35 15 12

≤

280 170 140

230 140

115

125

°

C

40 18 14

Uni

Ω

µ

t

A

509

IN74HC4053

AC ELECTRICAL CHARACTERISTICS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

t

PLH

, t

Maximum Propagation Delay, Channel-Select to

PHL

Analog Output (Figures 8 and 9)

t

PLH

, t

Maximum Propagation Delay , Analog Input to

PHL

Analog Output (Figures 10 and 11)

t

PLZ

, t

Maximum Propagation Delay , Enable to Analog

PHZ

Output (Figures 12 and 13)

t

PZL

, t

Maximum Propagation Delay , Enable to Analog

PZH

Output (Figures 12 and 13)

C

IN

Maximum Input Capacitance, Channel-Select or Enable Inputs

C

I/O

Maximum Capacitance Analog I/O All Switches Off

Common O/I - 50 50 50

Feedthrough - 1.0 1.0 1.0

V

CC

Guaranteed Limit

25 °C

≤85°

C≤125°C

Unit

to

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

370

74 63

60 12 10

290

58 49

345

69 59

465

93 79

75 15 13

364

73 62

435

87 74

550 110

94 90

18 15

430

86 73

515 103

87

ns

-101010pF

-353535pF

Power Dissipation Capacitance (Per Package) (Figure 15)

C

PD

Used to determine the no-load dynamic power consumption: P

D=CPDVCC

2

f+ICCV

CC

Typical @25°C,V

=5.0 V, VEE=0

CC

V

45 pF

510

IN74HC4053

ADDITIONAL APPLICATION CHARACTERISTICS

(GND = 0.0 V)

V

CC

Symbol Pa rameter Test Conditions V V

BW Maximum On-

Channel Bandwidth or Minimum Frequency

f

=1 MHz Sine Wave

in

Adjust f

Voltage to Obtain 0 dBm at V

in

Increase fin Frequence Until dB Meter Reads -3 dB

=50 Ω, CL=10 pF

R

L

OS

2.25

4.50

6.00 Response (Figure 5)

- Off-Channel Feedthrough Isolation (Figure 6)

f

= Sine Wave

in

Adjust f

Voltage to Obtain 0 dBm at V

in

fin = 10 kHz, RL =600 Ω, CL=50 pF

fin = 1.0 MHz, RL =50 Ω, CL=10 pF

IS

2.25

4.50

6.00

2.25

4.50

6.00

- Feedthrough Noise, Channel Select Input to Common O/I (Figure 7)

≤

V

1 MHz Square Wave (t

IN

Adjust R

at Setup so that IS= 0 A Enable

L

= GND

RL

= tf = 6 ns)

r

=600 Ω, CL=50 pF

2.25

4.50

6.00

RL =10 Ω, CL=10 pF

2.25

4.50

6.00

- Crosstalk Between Any Two Switches (Figure 14)

f

= Sine Wave

in

Adjust f

Voltage to Obtain 0 dBm at V

in

fin = 10 kHz, RL =600 Ω, CL=50 pF

IS

2.25

4.50

6.00

V

EE

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

Limit 25 °C

120 120 120

-50

-40

25 105 135

35 145 190

-50

*

Unit

MHz

dB

mVpp

dB

fin = 1 MHz, RL =50 Ω, CL=10 pF

THD Total Harmonic

Distortion (Figure 16)

f

= 1 kHz, RL =10 kΩ, CL=50 pF

in

THD = THD V V V

- THD

Measured

=4.0 VPP sine wave

IS

=8.0 VPP sine wave

IS

=11.0 VPP sine wave

IS

Source

* Limits not tested. Determined by design and verified by qualification.

2.25

4.50

6.00

2.25

4.50

6.00

-2.25

-4.50

-6.00

-2.25

-4.50

-6.00

-60

-60 %

0.10

0.08

0.05

511

IN74HC4053

Figure 1. On Resistance Test Set-Up

Figure 2. Maximum Off Channel Leakage

Current, Any One Channel, Test Set-U

P

Figure 4. Maximum On Channel Leakage

Current, Channel to Channel, Test Set-U

Figure 3. Maximum Off Channel Leakage Current,

Common Channel, Test Set-U

P

* Includes all probe and jig capacitance.

Figure 5. Maximum On Channel Bandwidth,

P

Test Set-U

P

* Includes all probe and jig capacitance.

Figure 6. Off Channel Feedthrough Isolation,

Test Set-U

P

512

* Includes all probe and jig capacitance.

Figure 7.Feedthrough Noise, Channel Select to Common

Out, Test Set-U

P

Figure 8. Switching Weveforms

* Includes all probe and jig capacitance.

Figure 9. Test Set-U

IN74HC4053

, Channel Select to Analog Out

P

* Includes all probe and jig capacitance.

Figure 10. Switching Weveforms

Figure 11. Test Set-U

, Analog In to Analog Out

P

Figure 12. Switching Weveforms Figure 13. Test Set-UP, Enable to Analog Out

513

IN74HC4053

* Includes all probe and jig capacitance.

Figure 14. Crosstalk Between Any Two

Switches, Test Set-U

p

Figure 16. Total Harmonic Distortion, Test Set-U

EXPANDED LOGIC DIAGRAM

Figure 15. Power Dissipation Capacitance, Test Set-U

P

p

514