Page 1
TECHNICAL DATA
Dual 4-Bit Shift Register
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two identical independent 4-stage serialinput/parallel-output registers. Each register has independent Clock
and Reset inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All register
stages are D-type, master-slave flip-flops. The logic level present at
the Data input is transferred into the first register stage and shifted
over one stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC4015
ORDERING INFORMATION
IN74HC4015N Plastic
IN74HC4015D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16 = V
PIN 8 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Clock Data Reset Q
LLLQ
HLHQ
XLQ
XX HLL
*
= No Change
X = don’t care
Q
0
*
Q
0
n-1
n-1
n
*
n
474
Page 2
IN74HC4015
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
V
=4.5 V
CC
=6.0 V
CC
and V
IN
should be constrained to the range
OUT
0
0
0
CC
1000
500
400
V
°
C
ns
CC
).
475
Page 3
IN74HC4015
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Inp ut
V
= 0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN= VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN= VIH or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
CC
Maximum Quiescent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
6.0 8.0 80 160
C
1.0
Unit
V
V
V
V
µ
A
µ
A
476
Page 4
IN74HC4015
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figure 2)
t
PLH
, t
Maximum Propagati on Delay, Clock to Q
PHL
(Figures 2 and 5)
t
PHL
Maximum Propagation Delay, Reset to Q (Figures
1 and 5)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 3 and 5)
C
IN
Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Latch)
C
PD
Used to determine the no-load dynamic power
consumption: P
D=CPDVCC
2
f+ICCV
CC
V
CC
25 °C to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6
30
35
175
35
30
205
41
35
75
15
13
Typical @25°C,V
Guaranteed Limit
≤85°C≤
4.8
24
28
220
44
37
255
51
43
95
19
16
=5.0 V
CC
125°C
4
20
24
265
53
45
310
62
53
110
22
19
140 pF
Unit
MHz
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
su
Minimum Setup Time, D to Clock
(Figure 4)
t
h
Minimum Hol d Time, Clock to D
(Figure 4)
t
rec
Minimum Recovery Time, Reset to
Clock (Figure 1)
t
t
tr, t
w
w
Minimum Pulse Width, Reset (Figure1)2.0
Minimum Pulse Width, Clock (Figure4)2.0
Maximum Inp ut Ris e and Fall Times
f
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
CC
Guaranteed Limit
25 °C to
-55°C
50
10
9.0
5
5
5
5
5
5
80
16
14
80
16
14
1000
500
400
≤85°
65
13
11
5
5
5
5
5
5
100
20
17
100
20
17
1000
500
400
≤
C
125°C
75
Unit
ns
15
13
5
ns
5
5
5
ns
5
5
120
ns
24
20
120
ns
24
20
1000
ns
500
400
477
Page 5
IN74HC4015
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit
478
Page 6
EXPANDED LOGIC DIAGRAM
IN74HC4015
479
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