Page 1
TECHNICAL DATA
349
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
High-Performance Silicon-Gate CMOS
The IN74HC323 is identical in pinout to the LS/ALS323. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC323 features a multiplexed parallel input/output data
port to active full 8-bit handling in a 20 pin package. Due to the large
output drive capability and the 3-state feature, this device is ideally
suited for interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both ModeSelect lines, S
1
and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be
clocked into the register. Reading out of the register can be
accomplished when the outputs are enabled. The active-low synchronous Reset overrides all other inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
IN74HC323
ORDERING INFORMATION
IN74HC323N Plastic
IN74HC323DW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
Page 2
IN74HC323
350
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
OUT
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
I
IN
DC Input Current, per Pin
±
20
mA
I
OUT
DC Output Current, per Pin
±
35
mA
I
CC
DC Supply Current, VCC and GND Pins
±
75
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types -55 +125
°
C
tr, t
f
Input Rise and Fall Time (Figure 1) VCC =2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
Page 3
IN74HC323
351
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
25 °C
to
-55°C
≤
85
°
C
≤
125
°
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low Level Input Voltage
V
OUT
=0.1 V or VCC-0.1 V
I
OUT
≤
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High-Level
Output Voltage
VIN=VIH or V
IL
I
OUT
≤
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or V
IL
I
OUT
≤
6.0 mA (P/Q)
I
OUT
≤
7.8 mA (P/Q)
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VIN=VIH or V
IL
I
OUT
≤
4.0 mA (Q’)
I
OUT
≤
5.2 mA (Q’)
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low-Level
Output Voltage
VIN= VIL or V
IH
I
OUT
≤
20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or V
IL
I
OUT
≤
6.0 mA (P/Q)
I
OUT
≤
7.8 mA (P/Q)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VIN=VIH or V
IL
I
OUT
≤
4.0 mA (Q’)
I
OUT
≤
5.2 mA (Q’)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum Input
Leakage Current
VIN=VCC or GND 6.0
±
0.1
±
1.0
±
1.0
µ
A
I
OZ
Maximum ThreeState Leakage
Current
(Q
A
thru QH)
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT=VCC
or GND
6.0
±
0.5
±
5.0
±
10
µ
A
I
CC
Maximum Qui escent
Supply Current
(per Package)
VIN=VCC or GND
I
OUT
=0µA
6.0 8 .0 80 160
µ
A
Page 4
IN74HC323
352
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C
to
-55°C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
t
PLH
, t
PHL
Maximum Propagati on Delay, Clock to QA’ or
Q
H
’ (Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PLH
, t
PHL
Maximum Propagati on Delay, Clock to QA or Q
H
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to Q
A
thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
, t
PZH
Maximum Propagation Delay , OE1, OE2, S1, or
S2 to Q
A
thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, QA thru Q
H
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
TLH
, t
THL
Maximum Output Transition Time, QA’ or QH’
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance - 10 10 10 pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
thru Q
H
-151515pF
Power Dissipation Capacitance (Per Package),
Outputs Enable
Typical @25°C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
240 pF
Page 5
IN74HC323
353
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25 °C to-55°C
≤85°
C
≤
125°C
Unit
t
su
Minimum Setup Time, Mod e Select
S1 or S2 to Clock (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
su
Minimum Setup Time, Data Inp uts
S
A
, SH, PA thru PH to Clock
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold T ime, Clock to Mode
Select S1 or S2 (Figure 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
t
h
Minimum Hold T ime, Clock to Data
Inputs, S
A
, SH, PA thru PH (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Clock (Figure1)2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
w
Minimum Pulse Width, Reset (Figure2)2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, t
f
Maximum Input Rise and Fa ll T imes
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Page 6
IN74HC323
354
FUNCTION TABLE
Inputs Response
Mode Reset Mode
Select
Output
Enables
Clock Serial
Inputs
PA/
Q
A
PB/
Q
B
PC/
Q
C
PD/
Q
D
PE/
Q
E
PF/
Q
F
PG/
Q
G
PH/
Q
H
QA’QH’
S2S1OE1 OE2 DAD
H
Reset L X L L L XXLLLLLLL L L L
L L X L L XXLLLLLLL L L L
LHHX X XXX QA through QH=Z L L
Shift
Right
H L H H X D X Shift Right: QA through QH=Z;
D
A
FA; FA FB; etc
DQ
G
H L H X H D X Shift Right: QA through QH=Z;
D
A
FA; FA FB; etc
DQ
G
H L H L L D X Shift Right: DA FA =QA;
F
A
FB =QB; etc
DQ
G
Shift
Left
H H L H X X D Shift Left: QA through QH=Z;
D
H
FH; FH FG; etc
Q
B
D
H H L X H X D Shift Left: QA through QH=Z;
D
H
FH; FH FG; etc
Q
B
D
H H L L L X D Shift Left: DH FH =QH;
F
H
FG =QG; etc
Q
B
D
Parallel
Load
H H H X X X X Parallel Load:P
N
F
N
PAP
H
Hold H L L H X X X X Hold: QA through QH=Z; FN=F
N
PAP
H
H L L X H X X X Hold: QA through QH=Z; FN=F
N
PAP
H
H L L L L X X X Hold: QN =Q
H
PAP
H
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-impedance
state; however, sequential operation or clearing of the register is not affected.
Page 7
IN74HC323
355
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3a. Switching Waveforms Figure 3b. Switching Waveforms
Figure 4. Switching Waveforms Figure 5. Test Circuit
Figure 6. Test Circuit
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