Datasheet IN74HC299DW Datasheet (INTEGRAL)

8-Bit Bidirectional Universal Shift Register with Parallel I/O

High-Performance Silicon-Gate CMOS

The IN74HC299 is identical in pinout to the LS/ALS299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The IN74HC299features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system.

Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both ModeSelect lines, S impedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 2.0 to 6.0 V

•

Low Input Current: 1.0 µA

•

High Noise Immunity Characteristic of CMOS Devices

and S2, high. This places the outputs in the high-

1

TECHNICAL DATA

IN74HC299

ORDERING INFORMATION

IN74HC299N Plastic

IN74HC299DW SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 20=V

PIN 10 = GND

CC

341

IN74HC299

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

I

OUT

I

CC

P

DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+

±

20

±

35

±

75

750 500

Tstg Storage Temperature -65 to +150

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mA mA mA

mW

°

C

°

C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

T

A

tr, t

f

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

DC Supply Voltage (Referenced to GND) 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

OUT

Operating Temperature, All Package Types -55 +125 Input Rise and Fall Time (Figure 1) VCC =2.0 V

IN

or V

OUT

)≤VCC.

V

CC

V

CC

and V

IN

=4.5 V

=6.0 V

OUT

should be constrained to the range

0 0 0

CC

1000

500 400

°

ns

V

C

CC

).

342

IN74HC299

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

Symbol Parameter Test Conditions V

V

OH

V

OL

I

IN

Minimum High-Level

IH

Input Voltage

Maximum Low -

IL

Level Input Voltage

Minimum High-Level Output Voltage

Maximum Low-Level Output Voltage

Maximum Input

V

=0.1 V or VCC-0.1 V

OUT



≤

I

20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT



 ≤

I

20 µA

OUT

VIN=VIH or V



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

VIN= VIL or V



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

VIN=VIH or V



 ≤

I

OUT



 ≤

I

OUT

IL

20 µA

IL

6.0 mA (P/Q)

7.8 mA (P/Q)

IL

4.0 mA (Q’)

5.2 mA (Q’)

IH

20 µA

IL

6.0 mA (P/Q)

7.8 mA (P/Q)

IL

4.0 mA (Q’)

5.2 mA (Q’)

VIN=VCC or GND 6.0

Leakage Current

I

OZ

Maximum ThreeState Leakage Current (Q

thru QH)

A

I

CC

Maximum Qui escent Supply Current

Output in High-Impedance State V

= V

or V

IN

IL

IH

V

OUT=VCC

or GND

VIN=VCC or GND

=0µA

I

OUT

(per Package)

V

CC

Guaranteed Limit

25 °C

to

≤

85

°

C

≤

125

°

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

3.98

5.48

0.1

0.26

±

0.1

±

0.5

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

3.84

5.34

0.1

0.33

±

1.0

±

5.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

3.7

5.2

0.1

0.4

±

6.0 8 .0 80 160

C

1.0

10

Unit

V

µ

A

µ

A

µ

A

343

IN74HC299

AC ELECTRICAL CHARACTERISTICS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

f

max

Maximum Clock Frequency (50 % Duty Cycle) (Figures 1 and 5)

t

PLH

t

, t

PHL

Maximum Propagati on Delay, Clock to QA’ or

PHL

Q

’ (Figures 1 and 5)

H

Maximum Propagati on Delay, Clock to QA thru

PHL

Q

(Figures 1 and 5)

H

Maximum Propagation Delay, Reset to QA’ or QH’ (Figures 2 and 5)

t

TLH

PLZ

PZL

t

PHL

, t

Maximum Propagation Delay, Reset to QA thru Q

(Figures 2 and 5)

H

Maximum Propagation Delay , OE1, OE2, S1, or

PHZ

S2 to Q

Maximum Propagation Delay , OE1, OE2, S1, or

PZH

S2 to Q

Maximum Output Transition Time, QA thru Q

THL

thru QH (Figures 3 and 6)

A

thru QH (Figures 3 and 6)

A

H

(Figures 1 and 5)

t

TLH

, t

Maximum Output Transition Time, QA’ thru QH’

THL

(Figures 1 and 5)

C

IN

C

OUT

Maximum Input Capacitance) - 10 10 10 pF Maximum Three-State I/O Capacitance

(I/O in High-Impedance State), Q

thru Q

A

H

V

CC

Guaranteed Limit

25 °C

≤85°C≤

125°C

Unit

to

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

5.0 25 29

170

34 29

160

32 27

175

35 30

190

38 32

150

30 26

150

30 26

60 12 10

75 15 13

4.0 20 24

215

43 37

200

40 34

220

44 37

240

48 41

190

38 33

190

38 33

75 15 13

95 19 16

3.4 17 20

255

51 43

240

48 41

265

53 45

285

57 48

225

45 38

225

45 38

90 18 15

110

22 19

MHz

ns

-151515pF

344

Power Dissipation Capacitance (Per Package),

Typical @25°C,V

=5.0 V

CC

Output Enable

C

PD

Used to determine the no-load dynamic power consumption: P

D=CPDVCC

2

f+ICCV

CC

240 pF

IN74HC299

TIMING REQUIREMENTS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

t

su

Minimum Setup Time, Mod e Select S1 or S2 to Clock (Figure 4)

t

su

Minimum Setup Time, Data Inp uts S

, SH, PA thru PH to Clock

A

(Figure 4)

t

h

Minimum Hold T ime, Clock to Mode Select S1 or S2 (Figure 4)

t

h

t

rec

Minimum Hold T ime, Clock to Data Inputs, S

, SH, PA thru PH (Figure 4)

A

Minimum Recovery Ti me, Reset Inactive to Clock (Figure 2)

t

tr, t

w

Minimum Pulse Width, Clock (Figure1)2.0

Minimum Pulse Width, Reset (Figure2)2.0

Maximum Input Rise and Fa ll T imes

f

(Figure 1)

V

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

CC

Guaranteed Limit

25 °C to-55°C

100

20 17

100

20 17

120

24 20

5 5 5

50 10

9

80 16 14

1000

500 400

≤85°

125

25 21

125

25 21

150

30 26

5 5 5

65 13 11

100

20 17

100

20 17

1000

500 400

≤

C

125°C

150

Unit

ns 30 26

150

ns 30 26

180

ns 36 31

5

ns

5 5

75

ns 15 13

120

ns 24 20

120

ns 24 20

1000

ns

500 400

345

IN74HC299

FUNCTION TABLE

Inputs Response

Mode Reset Mode

Select

S2S1OE1 OE2 DAD

Reset L X L L L X XXLLLLLLL L L L

L L X L L X XXLLLLLLL L L L LHHX X XXX QA through QH=Z L L

Shift

H L H H X D X Shift Right: QA through QH=Z;

Right

H L H X H D X Shift Right: QA through QH=Z;

H L H L L D X Shift Right: DA FA =QA;

Shift

H H L H X X D Shift Left: QA through QH=Z;

Left

H H L X H X D Shift Left: QA through QH=Z;

H H L L L X D Shift Left: DH FH =QH;

Parallel

H H H X X X X Parallel Load:P

Load Hold H L L H X X X X Hold: QA through QH=Z; FN=F

H L L X H X X X Hold: QA through QH=Z; FN=F H L L L L X X X Hold: QN =Q

Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high impedance state; however, sequential operation or clearing of the register is not affected.

Output

Enables

Clock Serial

Inputs

PA/

PB/

PC/

PD/

PE/

PF/

PG/

PH/

QA’QH’

Q

A

B

C

D

E

F

H

D

FA; FA FB; etc

A

D

FA; FA FB; etc

A

F

FB =QB; etc

A

D

FH; FH FG; etc

H

D

FH; FH FG; etc

H

F

FG =QG; etc

H

F

N

H

Q

G

H

DQ

G

DQ

G

DQ

G

D

Q

B

D

Q

B

D

Q

B

N

PAP

N

PAP

N

PAP

H

346

IN74HC299

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3a. Switching Waveforms Figure 3b. Switching Waveforms

Figure 4. Switching Waveforms Figure 5. Test Circuit

Figure 6. Test Circuit

347

IN74HC299

EXPANDED LOGIC DIAGRAM

348