Datasheet IN74HC251N, IN74HC251D Datasheet (INTEGRAL)

Page 1
8-Input Data Selector/Multiplexer with 3-State Outputs
High-Performance Silicon-Gate CMOS
The IN74HC251 is identical in pinout to the LS/ALS251. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
TECHNICAL DATA
IN74HC251
ORDERING INFORMATION
IN74HC251N Plastic
IN74HC251D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
FUNCTION TABLE
Inputs Outputs
A2 A1 A0 OE Y Y
XX X H Z Z L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7
D0,D1...D7=the level of the respective D input Z = high-impedance st ate X = don’t care
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Page 2
IN74HC251
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
25
±
50
±
75
750 500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA mA mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125 Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V V
and V
IN
=4.5 V
CC
=6.0 V
CC
should be constrained to the range
OUT
0 0 0
CC
1000
500 400
°
V
C
ns
CC
).
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Page 3
IN74HC251
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
 ≤
I
20 µA
OUT
VIN=VIH or V
 ≤
I
OUT
VIN=VIH or V
 ≤
I
OUT
 ≤
I
OUT
VIN=VIH or V
 ≤
I
OUT
VIN=VIH or V
 ≤
I
OUT
 ≤
I
OUT
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
OZ
I
CC
Maximum Three­State Leakage Current
Maximum Quiescent Supply Current
Output in High-Impedance State V
= VIL or V
IN
V
OUT=VCC
IH
or GND
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
±
0.5
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
±
5.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
1.0
±
6.0 8.0 80 160
C
10
Unit
V
V
V
V
µ
A
µ
A
µ
A
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Page 4
IN74HC251
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
PLH
, t
Maximum Propagation Delay, Input D to
PHL
Output Y or Y (Figures 1,2 and 5)
t
PLH
, t
Maximum Propagation Delay , Input A to
PHL
Output Y or Y (Figures 3 and 5)
t
PLZ
, t
Maximum Propagation Delay , Output Enable to
PHZ
Output Y (Figures 4 and 6)
t
PZL
, t
Maximum Propagation Delay , Output Enable to
PZH
Output Y (Figures 4 and 6)
t
PLZ
, t
Maximum Propagation Delay , Output Enable to
PHZ
Output Y (Figures 4 and 6)
t
PZL
, t
Maximum Propagation Delay , Output Enable to
PZH
Output Y (Figures 4 and 6)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 6)
C
IN
C
OUT
Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance
(Output in High-Impedance State)
V
CC
Guaranteed Limit
25 °C
≤85°C≤
125°C
Unit
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
185
37 31
205
41 35
195
39 33
145
29 25
220
44 37
150
30 26
75 15 13
230
46 39
255
51 43
245
48 42
180
36 31
275
55 47
190
38 33
95 19 16
280
56 48
310
62 53
295
59 50
220
44 38
330
66 56
225
45 38
110
22 19
ns
ns
ns
ns
ns
ns
ns
-151515pF
314
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power consumption: P
D=CPDVCC
2
f+ICCV
CC
Typical @25°C,V
36 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
=5.0 V
CC
Page 5
IN74HC251
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit Figure 6.Test Circuit
EXPANDED LOGIC DIAGRAM
315
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