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8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC166 is identical in pinout to the LS/ALS166. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or serial-in, serial-out shift register with
gated clock inputs and an overriding clear input. The shift/load input
establishes the parallel-in or serial-in mode. When high, this input
enables the serial data input and couples the eight flip-flops for serial
shifting with each clock pulse. Synchronous loading occurs on the next
clock pulse when this is low and the parallel data inputs are enabled.
Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input
positive NOR gate, which permits one input to be used as a clock
enable or c lock inhibit function. Clo cking is inhibited when either o f
the clock inputs are held high, holding either input low enables the
other clock input. T his will allow the system clock to b e fr ee r unning
and the register stopped on command with the other clock input. A
change from low-to-high on the clock inhibit input should only be
done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, andsets all flip-flop to
zero.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
TECHNICAL DATA
IN74HC166
ORDERING INFORMATION
IN74HC166N Plastic
IN74HC166D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
235
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IN74HC166
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
CC
V
CC
and V
IN
=4.5 V
=6.0 V
OUT
should be constrained to the range
0
0
0
CC
1000
500
400
V
°
C
ns
CC
).
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IN74HC166
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
CC
Maximum Qui escent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
6.0 8.0 80 160
C
1.0
Unit
V
V
V
V
µ
A
µ
A
FUNCTION TABLE
Inputs Internal
Outputs
Clear Shift/Load Clock
Inhibit
Clock S
A
Parallel
Q
Q
A
A...H
LXXXXXLLL
HXX XX No change
H L L X a...h a b h
HHL HXHQAnQ
HHL LXLQAnQ
HXHXXX No change
X = don’t care
a...h = the level of steady state input voltage at input A trough H respectively
Output
B
Q
H
Gn
Gn
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IN74HC166
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Minimum Clock Frequency (50 % D ut y Cycle)
(Figures 2 and 4)
t
PLH
t
, t
PHL
Maximum Propagation Delay, Clock (or Clock
PHL
Inhibit) to Q
(Figures 2,3 and 4)
H
Maximum Propagation Delay , Clear to Q
H
(Figures 1 and 4)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
C
IN
Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
V
CC
25 °C
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6.0
31
36
140
28
24
150
30
26
75
16
14
Typical @25°C,V
Guaranteed Limit
≤85°C≤
5.0
25
28
175
35
30
200
40
34
95
20
18
=5.0 V
CC
125°C
4.2
21
25
210
42
36
230
48
40
110
25
20
140 pF
Unit
MHz
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
su
Minimum Setup Time, Shift/Load to
Clock (Figure 3)
t
su
Minimum Setup Time, Data before
Clock (or Clock Inhibit) (F igure 3)
t
w
Minimum Pulse Width, Cl ock (or
Clock Inhibit) (Figure 2)
238
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
CC
Guaranteed Limit
25 °C to
-55°C
80
16
14
80
16
14
80
16
14
≤85°
100
20
18
100
20
18
100
20
17
≤
C
125°C
120
Unit
ns
24
20
120
ns
24
20
120
ns
24
20
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IN74HC166
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
239
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IN74HC166
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
240
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