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8-Bit Serial-Input/Parallel-Output
Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC164 is identical in pinout to the LS/ALS164. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC164 is an 8-bit, serial-input to parallel-output shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The active-low asynchronous Reset overrides theClock
and Serial Data inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
TECHNICAL DATA
IN74HC164
ORDERING INFORMATION
IN74HC164N Plastic
IN74HC164D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =V
PIN 7 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Reset Clock A1 A2 QA QB ... Q
L X X X L L ... L
H X X no change
H H D D QAn ... Q
H D H D QAn ... Q
D = data input
X = don’t care
Q
- Q
An
rising edge at the clock input.
= data shifted from the previous stage on a
Gn
H
Gn
Gn
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IN74HC164
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
25
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
CC
V
CC
and V
IN
=4.5 V
=6.0 V
OUT
should be constrained to the range
0
0
0
CC
1000
500
400
°
ns
V
C
CC
).
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IN74HC164
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
VIN= VIH or V
≤
I
OUT
VIN= VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
CC
Maximum Qui escent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
6.0 8.0 80 160
C
1.0
Unit
V
V
V
V
µ
A
µ
A
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IN74HC164
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Maximum Clock Frequency (50 % Duty Cycle)
(Figures 1 and 4)
t
PLH
, t
Maximum Propagati on Delay,Clock to Q (Figures
PHL
1 and 4)
t
PHL
Maximum Propagation Delay,Reset to Q (Figures
2 and 4)
t
TLH
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 4)
C
IN
Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
V
CC
25 °C
to
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6.0
30
35
175
35
30
205
41
35
75
15
13
Typical @25°C,V
Guaranteed Limit
≤85°
C≤125°C
4.8
24
28
220
44
37
255
51
43
95
19
16
CC
4.0
20
24
265
53
45
310
62
53
110
22
19
=5.0 V
140 pF
Unit
MHz
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
SU
Minimum Setup Time,A1 or
A2 to Clock (Figure 3)
t
h
Minimum Hold T ime, Clock
to A1 or A2 (Fig ure 3)
t
rec
Minimum Recovery Ti me,
Reset Inactive to Clock
(Figure 2)
t
w
Minimum Pulse W idth, Reset
(Figure 2)
t
w
Minimum Pulse W idth, Clock
(Figure 1)
t
r, tf
Maximum Input Rise and Fa ll
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
CC
25 °C to
-55°C
50
10
9
5
5
5
5
5
5
80
16
14
80
16
14
1000
500
400
Guaranteed Limit
≤85°
C
65
13
11
5
5
5
5
5
5
100
20
17
100
20
17
1000
500
400
≤
125°C
75
15
13
120
24
20
120
24
20
1000
500
400
Unit
ns
5
ns
5
5
5
ns
5
5
ns
ns
ns
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IN74HC164
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
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