Datasheet IN74HC03AD Datasheet (INTEGRAL)

Quad 2-Input NAND Gate with Open-Drain Outputs

High-Performance Silicon-Gate CMOS

The IN74HC03A is identical in pinout to the LS/ALS03. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The IN74HC03A NAND gate has, as its output, a highperformance MOS N-Channel transistor. This NAND gate can, therefore, with a suitable pullup resistor, be used in wired-AND applications.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 2.0 to 6.0 V

•

Low Input Current: 1.0 µA

•

High Noise Immunity Characteristic of CMOS Devices

TECHNICAL DATA

IN74HC03A

ORDERING INFORMATION

IN74HC03AN Plastic

IN74HC03AD SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN 14 =V

PIN 7 = GND

CC

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output AB Y LL Z LH Z HL Z HH L

Z= High Impedance

19

IN74HC03A

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

I

OUT

I

CC

P

DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+

±

20

±

25

±

50

750 500

Tstg Storage Temperature -65 to +150

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mA mA mA

mW

°

C

°

C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

T

A

tr, t

f

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open.

DC Supply Voltage (Referenced to GND) 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

OUT

Operating Temperature, All Package Types -55 +125 Input Rise and Fall Time (Figure 1) VCC =2.0 V

IN

or V

OUT

)≤VCC.

V

CC

V

CC

and V

IN

=4.5 V

=6.0 V

OUT

should be constrained to the range

0 0 0

CC

1000

500 400

V

°

C

ns

CC

).

20

IN74HC03A

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

Symbol Parameter Test Conditions V

V

OL

I

IN

Minimum High-Level

IH

Input Voltage

Maximum Low -

IL

Level Input Voltage

Maximum Low-Leve l Output Voltage

Maximum Input

V

=0.1 V or VCC-0.1 V

OUT



≤

I

20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT



 ≤

I

20 µA

OUT

VIN=V

IH



 ≤

I

20 µA

OUT

VIN=V

IH



 ≤

I

4.0 mA

OUT



 ≤

I

5.2 mA

OUT

VIN=VCC or GND 6.0

Leakage Current

I

CC

Maximum Quiesce nt Supply Current

VIN=VCC or GND

=0µA

I

OUT

(per Package)

I

OZ

Maximum ThreeState Leakage Current

Output in High-Impedance State V

= VIL or V

IN

I

= VCC or GND

OUT

IH

V

CC

Guaranteed Limit

25 °C

to

≤

85

°

C

≤

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.5

1.35

1.8

0.1

0.26

±

0.1

1.5

3.15

4.2

0.5

1.35

1.8

0.1

0.33

±

1.0

1.5

3.15

4.2

0.5

1.35

1.8

0.1

0.4

±

6.0 1.0 10 40

6.0

±

0.5

±

5.0

±

125

°

C

1.0

10

Unit

V

µ

A

µ

A

µ

A

21

IN74HC03A

AC ELECTRICAL CHARACTERISTICS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

t

PLZ

, t

Maximum Propagation Delay, Input A or B to

PZL

Output Y (Figures 1 and 2)

t

THL

Maximum Output Transition Time, Any Output (Figures 1 and 2)

C

IN

C

OUT

Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance

(Output in High-Impedance State)

Power Dissipation Capacitance (Per Gate)

C

PD

Used to determine the no-load dynamic power consumption: P

D=CPDVCC

2

f+ICCV

CC

V

CC

Guaranteed Limit

25 °C

≤85°C≤

125°C

Unit

to

-55°C

2.0

4.5

6.0

2.0

4.5

6.0

120

24 20

75 15 13

150

30 26

95 19 16

180

36 31

110

22 19

ns

-101010pF

Typical @25°C,V

=5.0 V

CC

8.0 pF

22

.Figure 1. Switching Waveforms Figure 2. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/4 of the Device)

*

Denotes ope n-drain outputs