Datasheet IN74ACT193N, IN74ACT193D Datasheet (INTEGRAL)

TECHNICAL DATA

295

Presettable 4-Bit Binary UP/DOWN Counter

High-Speed Silicon-Gate CMOS

The IN74ACT193 is identical in pinout to the LS/ALS192,
HC/HCT192. The IN74ACT193 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.

The counter ha s two separate clo ck inputs, a Co unt Up Cloc k and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset i nputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TC

D

) and Terminal Count Up (TCU) Outputs are provided to

enable cascading of both up and down counting functions. The TC

D

output produces a negative going pulse when the counter underflows
and TC

U

outputs a pulse when the counter overflows. The counter can

be cascaded by connecting the TC

U

and TCD outputs of one device to
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.

•

TTL/NMOS Compatible Input Levels

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 4.5 to 5.5 V

•

Low Input Current: 1.0 µA; 0.1 µA @ 25°C

•

Outputs Source/Sink 24 mA

IN74ACT193

ORDERING INFORMATION

IN74ACT193N Plastic

IN74ACT193D SOIC

TA = -40° to 85° C for all

packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16 =V

CC

PIN 8 = GND

IN74ACT193

296

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

V

IN

DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

V

OUT

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

I

IN

DC Input Current, per Pin

±

20

mA

I

OUT

DC Output Sink/Source Current, per Pin

±

50

mA

I

CC

DC Supply Current, VCC and GND Pins

±

50

mA

P

D

Power Dissipation in Still Air, Plastic DIP+
SOIC Package+

750
500

mW

Tstg Storage Temperature -65 to +150

°

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)

260

°

C

*

Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

DC Supply Voltage (Referenced to GND) 4.5 5.5 V

VIN, V

OUT

DC Input Voltage, Output Voltage (Referenced to GND) 0 V

CC

V

T

J

Junction Temperature (PDIP) 140

°

C

T

A

Operating Temperature, All Package Types -40 +85

°

C

I

OH

Output Current - High -24 mA

I

OL

Output Current - Low 24 mA

tr, t

f

Input Rise and Fall Time

*

(except Schmitt Inputs)

V

CC

=4.5 V

V

CC

=5.5 V

0
0

10

8.0

ns/V

*

VIN from 0.8 V to 2.0 V

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V

IN

and V

OUT

should be constrained to the range

GND≤(V

IN

or V

OUT

)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

).

Unused outputs must be left open.

IN74ACT193

297

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

V

CC

Guaranteed Limits

Symbol Parameter Test Conditions V

25 °C-40

°

C to

85°C

Unit

V

IH

Minimum High-Level
Input Voltage

V

OUT

=0.1 V or VCC-0.1 V 4 .5

5.5

2.0

2.0

2.0

2.0

V

V

IL

Maximum Low ­Level Input Voltage

V

OUT

=0.1 V or VCC-0.1 V 4 .5

5.5

0.8

0.8

0.8

0.8

V

V

OH

Minimum High-Level
Output Voltage

I

OUT

≤ -50 µA

4.5

5.5

4.4

5.4

4.4

5.4

V

*

VIN=VIH or V

IL

IOH=-24 mA
I

OH

=-24 mA

4.5

5.5

3.86

4.86

3.76

4.76

V

OL

Maximum Low- Level
Output Voltage

I

OUT

≤ 50 µA

4.5

5.5

0.1

0.1

0.1

0.1

V

*

VIN=V

IH

IOL=24 mA
I

OL

=24 mA

4.5

5.5

0.36

0.36

0.44

0.44

I

IN

Maximum Input
Leakage Current

VIN=VCC or GND 5.5

±

0.1

±

1.0

µ

A

I

OLD

+Minimum Dynamic
Output Current

V

OLD

=1.65 V Max 5.5 75 mA

I

OHD

+Minimum Dynamic
Output Current

V

OHD

=3.85 V Min 5.5 -75 mA

I

CC

Maximum Quiescent
Supply Current
(per Package)

VIN=VCC or GND 5.5 8.0 80

µ

A

*

All outputs loaded; thresholds on input associated with output under test.

+Maximum test duration 2.0 ms, one output loaded at a time.

FUNCTION TABLE

Inputs Mode

MR PL CP

U

CP

D

HX X X Reset(Asyn.)
L L X X Preset(Asyn.)
L H H No Count
L H H Count Up
L H H Count Down
L H H No Count

X = don’t care

The IN74ACT193 is an UP/DOWN MODULO-

16 Binary Counte r.

Logic equati ons
For Terminal Count:

TC

U

= Q0 • Q1 • Q2 • Q3 • CP

U

TCD = Q0 • Q1 • Q2 • Q3 • CP

D

IN74ACT193

298

AC ELECTRICAL CHARACTERISTICS

(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol Parameter

25 °C-40

°

C to

85°C

Unit

Min Max Min Max

f

max

Maximum Clock Frequency (Figur e 1) 100 80 MHz

t

PLH

Propagation Delay, CPU or CPD to TCU or TC

D

(Figure 2)

15 16.5 ns

t

PHL

Propagation Delay, CPU or CPD to TCU or TC

D

(Figure 2)

14 15.5 ns

t

PLH

Propagation Delay, CPU or CPD to Qn (Figure 1) 12 13.5 ns

t

PHL

Propagation Delay, CPU or CPD to Qn (Figure 1) 12 13.5 ns

t

PLH

Propagation Delay, Pn to Qn (Figure 3) 12 13.5 ns

t

PHL

Propagation Delay, Pn to Qn (Figure 3) 12 13.5 ns

t

PLH

Propagation Delay, PL to Qn (Figure 4) 12 13.5 ns

t

PHL

Propagation Delay, PL to Qn (Figure 4) 15 16.5 ns

t

PHL

Propagation Delay, MR to Qn (Figure 5) 15 16.5 ns

t

PLH

Propagation Delay, MR to TCU (Figure 6) 14 15.5 ns

t

PHL

Propagation Delay, MR to TCD (Figure 6) 14 15.5 ns

t

PLH

Propagation Delay, PL to TCU or TCD (Figure 6) 15 16.5 ns

t

PHL

Propagation Delay, PL to TCU or TCD (Figure 6) 11 12.5 ns

t

PLH

Propagation Delay, Pn to TCU or TCD (Figure 6) 15 16.5 ns

t

PHL

Propagation Delay, Pn to TCU or TCD (Figure 6) 15 16.5 ns

C

IN

Maximum Input Capacitance 4.5 4.5 pF

Typical @25°C,VCC=5.0 V

C

PD

Power Dissipation Capacitance 45 pF

IN74ACT193

299

TIMING REQUIREMENTS

(CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V ± 10%)

Guaranteed Limits

Symbol Parameter

25 °C-40

°

C to

85°C

Unit

t

su

Minimum Setup Time, Pn to PL (Figure 7) 8 9 ns

t

h

Minimum Hold Time, P L to Pn (Figure 7) -1.0 -1.0 ns

t

w

Minimum Pulse Width, PL (Figure 4) 14 15 ns

t

w

Minimum Pul se Width, CPU or CP

D

(Figure 1)

10 11 ns

t

w

Minimum Pulse Width, MR (Figure 5) 12 14 ns

t

rec

Minimum Recovery Time , PL to CPU or CPD (Figure

5)

89ns

t

rec

Minimum Recovery Time , MR to CPU or CPD (Figure

5)

14 16 ns

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms Figure 4. Switching Waveforms

IN74ACT193

300

Figure 5. Switching Waveforms Figure 6. Switching Waveforms

Figure 7. Switching Waveforms

TIMING DIAGRAM

IN74ACT193

301

EXPANDED LOGIC DIAGRAM