Page 1
TECHNICAL DATA
Presettable BCD/Decade UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The IN74ACT192 is identical in pinout to the LS/ALS192,
HC/HCT192. The IN74ACT192 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The counter ha s two separate clo ck inputs, a Co unt Up Cloc k and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When
the Parallel Load input is taken low the data is loaded independently of
either clock input. This feature allows the counters to be used as
devide-by-n by modifying the count lenght with the preset i nputs. In
addition the counter can also be cleared. This is accomplished by
inputting a high on the Master Reset input. All 4 internal stages are set
to low independently of either clock input.Both a Terminal Count
Down (TC
enable cascading of both up and down counting functions. The TC
output produces a negative going pulse when the counter underflows
and TC
be cascaded by connecting the TC
the Count Up Clock and Count Down Clock inputs, respectively, of the
next device.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
•
Outputs Source/Sink 24 mA
) and Terminal Count Up (TCU) Outputs are provided to
D
outputs a pulse when the counter overflows. The counter can
U
and TCD outputs of one device to
U
ORDERING INFORMATION
IN74ACT192N Plastic
IN74ACT192D SOIC
TA = -40° to 85° C for all
D
PIN ASSIGNMENT
IN74ACT192
packages
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
281
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IN74ACT192
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
50
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
J
T
A
I
OH
I
OL
tr, t
f
*
VIN from 0.8 V to 2.0 V
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Junction Temperature (PDIP) 140
Operating Temperature, All Package Types -40 +85
Output Current - High -24 mA
Output Current - Low 24 mA
Input Rise and Fall Time
(except Schmitt Inputs)
IN
or V
OUT
)≤VCC.
*
V
V
=4.5 V
CC
=5.5 V
CC
and V
IN
0
0
should be constrained to the range
OUT
10
8.0
CC
V
°
C
°
C
ns/V
CC
).
282
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IN74ACT192
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
Minimum High-Level
IH
V
=0.1 V or VCC-0.1 V 4 .5
OUT
Input Voltage
V
Maximum Low -
IL
V
=0.1 V or VCC-0.1 V 4 .5
OUT
Level Input Voltage
V
OH
Minimum High-Level
I
OUT
≤ -50 µA
Output Voltage
*
VIN=VIH or V
IL
IOH=-24 mA
I
=-24 mA
OH
V
OL
Maximum Low- Level
I
OUT
≤ 50 µA
Output Voltage
*
VIN=V
IH
IOL=24 mA
I
=24 mA
OL
I
IN
Maximum Input
VIN=VCC or GND 5.5
Leakage Current
I
OLD
+Minimum Dynamic
V
=1.65 V Max 5.5 75 mA
OLD
Output Current
I
OHD
+Minimum Dynamic
V
=3.85 V Min 5.5 -75 mA
OHD
Output Current
I
CC
Maximum Quiescent
VIN=VCC or GND 5.5 8.0 80
Supply Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
V
5.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
CC
Guaranteed Limits
25 °C-40
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
°
C to
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
Unit
V
V
V
V
µ
A
µ
A
FUNCTION TABLE
Inputs Mode
MR PL CP
HX X X Reset(Asyn.)
L L X X Preset(Asyn.)
L H H No Count
L H H Count Up
L H H Count Down
L H H No Count
X = don’t care
CP
U
D
The IN74ACT192 can be preset to any state, but
will not count beyond 9. If preset to state 10, 11, 12,
13, 14 or 15, it will follow the sequence 10, 11, 6: 12,
13, 4: 14, 15, 2 if counting Up, and follow the
sequence 15, 14, 13, 12, 11, 10, 9 if counting Down.
Logic equati ons
For Terminal Count:
TC
= Q0 • Q3 • CP
U
TCD = Q0 • Q1 • Q2 • Q3 • CP
U
D
283
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IN74ACT192
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PLH
PHL
PLH
PHL
PLH
PHL
IN
Maximum Clock Frequency (Figur e 1) 100 80 MHz
Propagation Delay, CPU or CPD to TCU or TC
(Figure 2)
Propagation Delay, CPU or CPD to TCU or TC
(Figure 2)
Propagation Delay, CPU or CPD to Qn (Figure 1) 12 13.5 ns
Propagation Delay, CPU or CPD to Qn (Figure 1) 12 13.5 ns
Propagation Delay, Pn to Qn (Figure 3) 12 13.5 ns
Propagation Delay, Pn to Qn (Figure 3) 12 13.5 ns
Propagation Delay, PL to Qn (Figure 4) 12 13.5 ns
Propagation Delay, PL to Qn (Figure 4) 15 16.5 ns
Propagation Delay, MR to Qn (Figure 5) 15 16.5 ns
Propagation Delay, MR to TCU (Figure 6) 14 15.5 ns
Propagation Delay, MR to TCD (Figure 6) 14 15.5 ns
Propagation Delay, PL to TCU or TC
D
(Figure 6)
Propagation Delay, PL to TCU or TC
D
(Figure 6)
Propagation Delay, Pn to TCU or TCD (Figure 6) 15 16.5 ns
Propagation Delay, Pn to TCU or TCD (Figure 6) 15 16.5 ns
Maximum Input Capacitance 4.5 4.5 pF
(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
25 °C-40
°
C to
85°C
Min Max Min Max
D
D
15 16.5 ns
14 15.5 ns
15 16.5 ns
11 12.5 ns
Unit
284
Typical @25°C,VCC=5.0 V
C
PD
Power Dissipation Capacitance 45 pF
Page 5
IN74ACT192
TIMING REQUIREMENTS
(CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V ± 10%)
Symbol Parameter
t
su
t
h
t
w
t
w
Minimum Setup Time, Pn to PL (Figure 7) 8 9 ns
Minimum Hold Time, P L to Pn (Figure 7) -1.0 -1.0 ns
Minimum Pulse Width, PL (Figure 4) 14 15 ns
Minimum Pul se Width, CPU or CP
(Figure 1)
t
w
t
rec
Minimum Pulse Width, MR (Figure 5) 12 14 ns
Minimum Recovery Time , PL to CPU or CPD (Figure
5)
t
rec
Minimum Recovery Time , MR to CPU or CPD (Figure
5)
Guaranteed Limits
25 °C-40
°
C to
Unit
85°C
D
10 11 ns
89ns
14 16 ns
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
285
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IN74ACT192
Figure 5. Switching Waveforms Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
TIMING DIAGRAM
286
Page 7
EXPANDED LOGIC DIAGRAM
IN74ACT192
287
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