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Quad 3-State Noninverting Buffers
High-Speed Silicon-Gate CMOS
The IN74ACT125 is identical in pinout to the LS/ALS125,
HC/HCT125. The IN74ACT125 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The IN74ACT125 noninverting buffers are designed to be used with 3state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are active-low.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
•
Outputs Source/Sink 24 mA
TECHNICAL DATA
IN74ACT125
ORDERING INFORMATION
IN74ACT125N Plastic
IN74ACT125D SOIC
TA = -40° to 85° C for all packages
LOGIC DIAGRAM
PIN 14 =V
PIN 7 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
AOE Y
HL H
LL L
XH Z
X = don’t care
Z = high impedance
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IN74ACT125
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
50
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
J
T
A
I
OH
I
OL
tr, t
f
*
VIN from 0.8 V to 2.0 V
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Junction Temperature (PDIP) 140
Operating Temperature, All Package Types -40 +85
Output Current - High -24 mA
Output Current - Low 24 mA
Input Rise and Fall Time
(except Schmitt Inputs)
IN
or V
OUT
)≤VCC.
*
V
V
=4.5 V
CC
=5.5 V
CC
and V
IN
0
0
should be constrained to the range
OUT
10
8.0
CC
V
°
C
°
C
ns/V
CC
).
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IN74ACT125
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
Minimum High-Level
IH
V
= VCC-0.1 V 4.5
OUT
Input Voltage
V
Maximum Low -
IL
V
=0.1 V 4.5
OUT
Level Input Voltage
V
OH
Minimum High-Level
I
OUT
≤ -50 µA
Output Voltage
*
VIN=V
IH
IOH=-24 mA
I
=-24 mA
OH
V
OL
Maximum Low-Level
I
OUT
≤ 50 µA
Output Voltage
*
VIN= V
IL
IOL=24 mA
I
=24 mA
OL
I
IN
Maximum Input
VIN=VCC or GND 5.5
Leakage Current
∆
I
CCT
I
OZ
Additional Max.
I
/Input
CC
Maximum ThreeState Leakage
Current
I
OLD
+Minimum Dynamic
V
IN=VCC
V
IN
V
IN =VCC
V
OUT =VCC
V
OLD
- 2.1 V 5.5 1.5 mA
(OE)= VIH or V
IL
or GND
or GND
=1.65 V Max 5.5 75 mA
Output Current
I
OHD
+Minimum Dynamic
V
=3.85 V Min 5.5 -75 mA
OHD
Output Current
I
CC
Maximum Quiescent
VIN=VCC or GND 5.5 8.0 80
Supply Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
V
5.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
CC
Guaranteed Limits
25 °C-40
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
±
0.5
°
C to
85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
±
5.0
Unit
V
V
V
V
µ
A
µ
A
µ
A
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IN74ACT125
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
t
t
t
t
t
t
C
C
PLH
PHL
PZH
PZL
PHZ
PLZ
IN
PD
Propagation Delay, Input A to Output Y (Figure 1) 1.0 9.0 1.0 10.0 ns
Propagation Delay, Input A to Output Y (Figure 1) 1.0 9.0 1.0 10.0 ns
Propagation Delay, Output Enable toY (Figure 2) 1.0 8.5 1.0 9.5 ns
Propagation Delay, Output Enable toY (Figure 2) 1.0 9.5 1.0 10.5 ns
Propagation Delay, Output Enable toY (Figure 2) 1.0 9.5 1.0 10.5 ns
Propagation Delay, Output Enable toY (Figure 2) 1.0 10.0 1.0 10.5 ns
Maximum Input Capacitance 4.5 4.5 pF
Power Dissipation Capacitance 45 pF
(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
25 °C-40
°
C to 85°C
Min Max Min Max
Typical @25°C,VCC=5.0 V
Unit
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
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