Page 1
TECHNICAL DATA
Octal 3-State Bus Transceivers
and D Flip-Flops
High-Speed Silicon-Gate CMOS
The IN74AC652 is identical in pinout to the LS/ALS652,
HC/HCT652. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
These devices consists of bus transceiver circuits, D-type flip-flop,
and control circuitry arranged for multiplex transmission of data
directly from the data bus or from the internal storage registers.
Direction and Output Enable are provided to select the read-time or
stored data function. Data on the A or B Data bus, or both, can be
stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of
the select or enable or enable control pins. When A-to-B Source and
B-to-A Source are in the real-time transfer mode, it is also possible to
store data without using the internal D-type flip-flops by
simultaneously enabling Direction and Output Enable. In this
configuration each output reinforces its input. Thus, when all other
data sources to the two sets of bus lines are at high impedance, each set
of bus lines will remain at its last state.
The IN74AC652 has noninverted outputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA, 0.1 µA @ 25°C
•
High Noise Immunity Characteristic of CMOS Devices
•
Outputs Source/Sink 24 mA
IN74AC652
ORDERING INFORMATION
IN74AC652N Plastic
IN74AC652DW SOIC
TA = -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
PIN 12 = GND
CC
532
Page 2
IN74AC652
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
50
±
50
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
J
T
A
I
OH
I
OL
tr, t
f
*
VIN from 30% to 70% V
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Junction Temperature (PDIP) 140
Operating Temperature, All Package Types -40 +85
Output Current - High -24 mA
Output Current - Low 24 mA
Input Rise and Fall Time
(except Schmitt Inputs)
IN
or V
OUT
)≤VCC.
CC
*
V
V
V
=3.0 V
CC
=4.5 V
CC
=5.5 V
CC
and V
IN
0
0
0
should be constrained to the range
OUT
CC
150
40
25
V
°
C
°
C
ns/V
CC
).
533
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IN74AC652
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
Minimum High-Level
IH
V
=0.1 V or VCC-0.1 V 3 .0
OUT
Input Voltage
V
Maximum Low -
IL
V
=0.1 V or VCC-0.1 V 3 .0
OUT
Level Input Voltage
V
OH
Minimum High-Level
I
OUT
≤ -50 µA
Output Voltage
*
VIN=VIH or V
IL
IOH=-12 mA
I
=-24 mA
OH
I
=-24 mA
OH
V
OL
Maximum Low-Level
I
OUT
≤ 50 µA
Output Voltage
*
VIN=VIH or V
IL
IOL=12 mA
I
=24 mA
OL
I
=24 mA
OL
I
IN
Maximum Input
VIN=VCC or GND 5.5
Leakage Current
I
I
OZ
OLD
Maximum ThreeState Leakage
Current
+Minimum Dynamic
VIN(OE)=VIH or V
IL
VIN=VCC or GND
V
OUT=VCC
V
OLD
or GND
=1.65 V Max 5.5 75 mA
Output Current
I
OHD
+Minimum Dynamic
V
=3.85 V Min 5.5 -75 mA
OHD
Output Current
I
CC
Maximum Quiescent
VIN=VCC or GND 5.5 8.0 80
Supply Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: I
IN
and I
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
V
4.5
5.5
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
CC
Guaranteed Limits
25 °C-40
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±
0.1
±
0.6
°
C to
85°C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±
1.0
±
6.0
CC
Unit
V
V
V
V
µ
A
µ
A
µ
A
534
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IN74AC652
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=3.0 ns)
Symbol Parameter V
t
PLH
Propagation Delay, A-to-B Clock or
B-to-A Clock to A or B Data Port (Figure 1)
t
PHL
Propagation Delay, A-to-B Clock or
B-to-A Clock to A or B Data Port (Figure 1)
t
PLH
Propagation Delay, Input A to Output B or
Input B to Output A (Figures 2,3)
t
PHL
Propagation Delay, Input A to Output B or
Input B to Output A (Figures 2,3)
t
PLH
Propagation Delay, A-to-B Source or
B-to-A Source to A or B Data Port (Figure 4)
t
PHL
Propagation Delay, A-to-B Source or
B-to-A Source to A or B Data Port (Figure 4)
t
PZH
Propagation Delay, Output Enable to A Data
Port (Figure 5)
t
PZL
Propagation Delay, Output Enable to A Data
Port (Figure 5)
t
PHZ
Propagation Delay, Output Enable to A Data
Port (Figure 5)
t
PLZ
Propagation Delay, Output Enable to A Data
Port (Figure 5)
t
PZH
Propagation Delay, Direction to B Data Port
(Figure 6)
t
PZL
Propagation Delay, Direction to B Data Port
(Figure 6)
t
PHZ
Propagation Delay, Direction to B Data Port
(Figure 6)
t
PLZ
Propagation Delay, Direction to B Data Port
(Figure 6)
C
IN
C
OUT
Maximum Input Capacitance 5.0 4.5 4.5 pF
Input/Output Capacitance 5.0 15 15 pF
V
CC
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
*
Guaranteed Limits
25 °C-40
Min Max Min Max
4.0
2.5
3.0
2.0
3.0
2.0
2.5
1.5
3.0
2.5
2.5
2.0
2.5
1.5
2.5
1.5
3.0
2.0
2.5
2.0
3.0
2.0
2.5
1.5
3.5
2.5
3.0
2.5
17.0
12.0
14.5
10.5
14.0
9.5
13.0
9.0
14.0
10.0
13.5
10.0
12.0
9.0
12.0
9.0
13.0
11.0
12.5
10.5
12.5
9.5
12.5
9.5
13.5
11.5
13.5
11.5
3.0
2.0
2.5
1.5
2.5
1.5
2.0
1.0
2.5
2.0
2.0
1.5
2.0
1.0
2.0
1.0
2.5
1.5
2.0
1.5
2.5
1.5
2.0
1.0
3.0
2.0
2.5
2.0
°
C to
85°C
19.0
14.0
16.5
12.0
16.0
11.0
15.0
10.5
16.0
11.5
15.5
11.5
13.5
10.0
14.0
10.5
14.0
12.0
14.0
12.0
14.0
10.5
14.5
11.0
14.5
12.5
15.0
13.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
PD
*
Voltage Range 3.3 V is 3.3 V ±0.3 V
Power Dissipation Capacitance 60 pF
Voltage Range 5.0 V is 5.0 V ±0.5 V
Typical @25°C,VCC=5.0 V
535
Page 5
IN74AC652
TIMING REQUIREMENTS
(CL=50pF, Input tr=tf=3.0 ns)
Symbol Parameter V
t
su
Minimum Set up Time, A or B Data Port to Ato-B Clock or B-to-A Clock (Figure 7)
t
h
Minimum Hold Time, A-to-B Clo ck or
B-to-A Clock to A or B Data Port (Figure 7)
t
w
Minimum Pulse Width, A-to-B Clock or
B-to-A Clock (Fi gure 7)
TIMING DIAGRAM
*
V
CC
Guaranteed Limits
25 °C-40
°
C to
85°C
5.0 7.0 8.0 ns
5.0 2.5 2.5 ns
5.0 6.0 7.0 ns
Unit
536
Page 6
IN74AC652
FUNCTION TABLE
Dir. OE CAB CBA SAB SBA A B FUNCTION
INPUTS INPUTS Both the A bus and the B bus are inputs.
L H X X X X Z Z The output functions of the A and B bus
are disabled.
X X INPUTS INPUTS Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
OUTPUTS INPUTS The A bus are outputs and the B bus are
inputs.
*
X
LLX
X
X
HH X*LX L
H L X X H H Qn Qn The data stored to the internal flip-flops
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH
TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY
LOW TO TRANSITION OF THE CLOCK INPUTS
XXL L
*
XL L
H
H
L
H
L
H
The data at the B bus are displayed at the
A bus.
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
*
X X H Qn X The data stored to the internal flip-flops,
are displayed at the A bus.
*
XH H
L
H
L
The data at the B bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus are
outputs.
XX*LX L
H
H
L
H
L
H
The data at the A bus are displayed at the
B bus.
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
XX*H X X Qn The data stored to the internal flip-flops
are displayed at the B bus.
*
X
HX L
H
L
H
The data at the A bus are stored to the
internal flip-flops on low to high
transition of the clock pulse. The states of
the internal flip-flops output directly to
the B bus.
OUTPUTS OUTPUT S Both the A bus and the B bus are outputs
are displayed at the A and B bus
respectively.
H H Qn Qn The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
537
Page 7
IN74AC652
SWITCHING DIAGRAMS
Figure 1. Switching Waveforms
Figure 2. A Data Port = Input, B Data Port =
Output
Figure 4. Switching Waveforms Figure 5. Switching Waveforms
Figure 3. A Data Port = Output, B Data Port =
Input
538
Figure 6. Switching Waveforms Figure 7. Switching Waveforms
Page 8
EXPANDED LOGIC DIAGRAM
IN74AC652
539
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