Datasheet ILX554A Datasheet (Sony)

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ILX554A

2048-pixel CCD Linear Sensor (B/W) for Single 5V Power Supply Bar-code Reader

Description

The ILX554A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use.

Features

• Number of effective pixels: 2048 pixels

• Pixel size: 14µm × 56µm

(14µm pitch)

• Single 5V power supply

• Ultra-high sensitivity

• Built-in timing generator and clock-drivers

• Built-in sample-and-hold circuit

• Maximum clock frequency: 2MHz

Block Diagram

22 pin DIP (Cer-DIP)

D40 D39

Readout gate

pulse generator

φROGφCLK

Absolute Maximum Ratings

• Supply voltage VDD 6V

• Operating temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top Vie w)

OUT

SHSW

φCLK

φROG

2048

GND

D33

S2048 S2047 S2046

Readout gate

S3 S2 S1

D32

D2 D1

• Output amplifier

OUT

CCD analog shift register

• S/H circuit

Clock-drivers

Mode selector

Clock pulse generator/

Sample-and-hold pulse generator

19 20 114

SHSW

GND

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E00818-PS

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Pin Description

ILX554A

Pin No. Symbol

OUT

SHSW

φCLK

NC 10 11

φROG

Mode Description

Mode in use

With S/H

Without S/H

Description Signal output NC NC Switch (with S/H or without S/H) Clock pulse input NC NC NC NC NC Readout gate pulse input

Pin 4 (SHSW)

GND

VDD

Pin No.

12 13 14 15 16 17 18 19 20 21 22

Symbol Description NC NC NC NC NC NC NC GND VDD NC NC

NC NC NC NC NC NC NC GND 5V power supply NC NC

Recommended Supply voltage

Item Min.

VDD 4.5

Input Clock voltage Condition

Item Min. VIH VIL

∗1

This is applied to the all pulses applied externally. (φCLK, φROG)

4.5 0

Typ.

5.0

Typ.

5.0

—

∗∗

∗1

∗∗

Max.

5.5

Max.

VDD

0.5

Unit

V V

Clock Characteristics

Item Min. Input capacity of φCLK Input capacity of φROG

Symbol CφCLK CφROG

— —

Typ.

10 10

Max.

— —

Unit

pF pF

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Electro-optical Characteristics

(Ta = 25°C, VDD = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Without S/H mode)

ILX554A

Item Min. Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5V current consumption Total transfer efficiency Output impedance Offset level

Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS

180

— —

0.8

— — — — — —

— —

Typ. 240

3500

5.0

1.0

3.0

6.0 1

333

0.004

5.0

98.0 250

2.85

Max.

300

—

10.0

—

6.0

12.0

— — —

Unit V/(lx · s) V/(lx · s)

V mV mV

—

lx · s

Ω

Note)

1. For the sensitivity test light is applied with a uniform intensity of illumination.

2. Light sourse: LED λ = 660nm

3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.

Remarks

Note 1 Note 2 Note 3

—

Note 4 Note 4 Note 5 Note 6 Note 7

— — —

Note 8

PRNU = × 100 [%]

(VMAX – VMIN)/2

VAVE

The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE.

4. Integration time is 10ms.

5. Typical value is used for clock pulse and readout pulse. VOUT = 500mV.

6. DR =

VSAT

VDRK

When optical integration time is shorter, the dynamic range sets wider because dark voltage is in proportion to optical integration time.

7. SE =

VSAT

8. VOS is defined as indicated below.

Vout

DD D SI

GND

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Clock Timing Diagram (without S/H mode)

φROG

φCLK

123

2088

– 4 –

D1D2D3D4D5

∗

OUT

∗

Without S/H mode (4 pin → V

D10

D11

D12

D13

D14

D30

D31

D32S1S2S3S4

Optical black

(18 pixels)

1-line output period (2088 pixels)

DD)

Effective picture elements signal

(2048 pixels)

S2045

S2046

S2047

S2048

D33

D34

D35

Dummy signal

(8 pixels)Dummy signal (32 pixels)

D36

D37

D38

D39

D40

Note) 2090 or more clock pulse are required.

ILX554A

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Clock Timing Diagram (with S/H mode)

φROG

φCLK

123

2088

– 5 –

D0D1D2D3D4

∗

OUT

∗

With S/H mode (4 pin → GND)

D10

D11

D12

Optical black

D13

D14

D30

(18 pixels)

1-line output period (2089 pixels)

D31

D32

Effective picture elements signal

(2048 pixels)

S2045

S2046

S2047

S2048

D33

D34

D35

Dummy signal

(8 pixels)Dummy signal (33 pixels)

D36

D37

D38

D39

D40

Note) 2090 or more clock pulse are required.

ILX554A

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φφ

φCLK Timing (For all modes)

φφ

φCLK

ILX554A

t1 t2

t3 t4

Item

φCLK pulse rise/fall time φCLK pulse duty

∗1

100 × t4 / (t3 + t4)

φφ

φROG,

φφ

φCLK Timing

φφ

∗1

φROG

φCLK

Symbol

t1, t2

—

t5 t9

Min.

Typ.

10 50

Max.

100

Unit

Item

φROG, φCLK pulse timing 1 φROG, φCLK pulse timing 2 φROG pulse rise/fall time φROG pulse period

Symbol

t5 t9

t6, t8

– 6 –

Min.

1000

Typ. 3000 3000

5000

Max.

— — — —

Unit

ns ns ns ns

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φφ

φCLK, VOUT Timing (Note 1)

φφ

φCLK

OUT

∗

OUT

(Note 2)

ILX554A

(Note 3)

t11t10

t12

Item

φCLK-VOUT 1 φCLK-VOUT 2 φCLK-VOUT∗ (with S/H) 3

Symbol

t10 t11 t12

Min.

20 55 20

Typ.

Note 1) fck = 1MHz, φCLK pulse duty = 50%, φCLK pulse rise/fall time = 10ns Note 2) Output wavefor m when inter nal S/H is in use. Note 3) indicates the correspondence of clock pulse and data period.

100 210 150

Max.

250 410 250

Unit

ns ns ns

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Example of Representative Characteristics

Spectral sensitivity (Typ.) (Ta = 25˚C)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1 0

400 500 600 700

ILX554A

800 900 1000

Wavelength [nm]

Dark voltage rate vs. Ambient temperature (Typ.)

Dark voltage rate

0.1 01020

Ta – Ambient temperature [˚C]

30 40 50 60

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ILX554A

Output voltage rate vs. Integration time (Typ.)

Output voltage rate

0.1 1

Integration time [ms]

Offset level vs. VDD (Typ.)

3.2

Current consumption rate vs. Clock frequency (Typ.)

2.0

1.5

1.0

Current consumption rate

0.5

100 0

3.2

1.00.5 1.5

Clock frequency [MHz]

2.0

Offset level vs. Ambient temperature (Typ.)

3.1

3.0

2.9

2.8

Offset level [V]

2.7

2.6

2.5

2.4

4.50

5.004.75 5.25

VDD [V]

5.50

3.1

3.0

2.9

2.8

Offset level [V]

2.7

2.6

2.5

2.4 0

20 40

Ambient temperature [˚C]

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ILX554A

Application Circuit (Without S/H mode)

0.01µ

3kΩ

OUT

22µ/10V

Note)

GND

SHSW

φCLK

OUT

1 2 3 4 5 6

100Ω

φCLK

171819202122

7 8 9 10 11

1213141516

φROG

100Ω

φROG

Note) This circuit diagram is the case when internal S/H mode is not used.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

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Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling, be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive

shoes. b) When handling directly use an eath band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) lonized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates use cartons treated for the prevention of static charges.

2) Notes on handling CCD Cer-DIP package The following points should be observed when handling and installing this package. a) (1) Compressive strength: 39N/surface

(Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm

ILX554A

Upper ceramic layer 39N

Lower ceramic layer

(1)

Low-melting glass

29N

(2)

29N

(3)

0.9Nm

(4)

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the glass to crack because the upper and lower ceramic

layers are shielded by low-melting glass. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a solder ing iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such

as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes demage to the glass abd other defects. Use a grounded

30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount image sensors, do not use a solder suction equipment. When using an electric desoldering

tool, ground the controller. For the control system, use a zero cross type.

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ILX554A

4) Dust and dir t protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface blow it off with an air blower. (For dirt stuck through static electricity, ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

7) Normal output signal is not obtained immediately after device switch on. Use the output signal added 22500 pulses or above to φCLK clock pulse.

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Package Outline Unit: mm

6.46 ± 0.5

28.672 (14µm X 2048Pixels)

22 pin DIP (400mil)

41.6 ± 0.5

0˚ to 9˚

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Sony Corporation

No.1 Pixel

5.0 ± 0.3

4.0 ± 0.5

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREA TMENT LEAD MATERIAL PACKAGE MASS

DRAWING NUMBER

2.54 0.51

Cer-DIP TIN PLATING 42 ALLOY

5.20g LS-A20(E)

0.3

3.65

10.0 ± 0.5

0.25

1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm.

2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.

4.35 ± 0.5

ILX554A