Datasheet ILX553A Datasheet (Sony)

Page 1
5150-pixel CCD Linear Sensor (B/W)
Description
Features
• Number of effective pixels: 5150 pixels
• Pixel size: 7µm × 7µm (7µm pitch)
• Clamp circuit is on-chip
• Ultra high sensitivity/Ultra low lag
• Maximum data rate: 16MHz
• Single 12V power supply
• Input clock pulse: CMOS 5V drive
• Package: 22 pin Plastic DIP (400mil)
ILX553A
22 pin DIP (Plastic)
Block Diagram
φROG 16
Absolute Maximum Ratings
• Supply voltage VDD 15 V
• Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
GND
GND
GND
GND
V
OUT
VDD
GND
φ1
GND
GND
GND
10
11
1
2
3
4
5
6
7
8
9
1
5150
22
21
20
19
18
17
16
15
14
13
12
GND
GND
φLH
φRS
GND
φCLP
φROG
φ2
GND
GND
GND
φ2
φLH
DD
V
15
20
6
Driver
D
D64
S5150
S1
Read out gate
D63
D15 D14
CCD register
5
OUT
V
8
19
17
φ1
φRS
φCLP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00X48-PS
Page 2
Pin Description
ILX553A
Pin No. Symbol Description
1 2 3 4 5 6 7 8
9 10 11
GND GND GND GND VOUT VDD GND φ1 GND GND GND
GND GND GND GND Signal out 12V power supply GND Clock pulse input GND GND GND
Recommended Supply Voltag e
Item Min.
VDD 11.4
Typ.
12.0
Max.
12.6
Pin No. Symbol Description
12 13 14 15 16 17 18 19 20 21 22
GND GND GND
φ2 φROG φCLP
GND
φRS φLH
GND GND
GND GND GND Clock pulse input Clock pulse input Clock pulse input GND Clock pulse input Clock pulse input GND GND
Unit
V
Clock Characteristics
Item Min. Input capacity of φ1, φ2 Input capacity of φLH Input capacity of φRS
∗1
∗1
Input capacity of φCLP Input capacity of φROG
Symbol Cφ1, Cφ2 CφLH CφRS
∗1
CφCLP CφROG
— — — — —
Typ.
400
10 10 10 10
Clock Frequency
Item Min.
φ1, φ2, φLH, φRS, φCLP —
fφ1, fφ2, fφLH, fφRS, fφCLP
Symbol
Input Clock Pulse Voltage Condition
Item
φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage
High level Low level
Min.
4.75 0
Typ.
5.0
—
Max.
— — — — —
Max.
5.25
0.1
Typ.
1
Unit
pF pF pF pF pF
Unit
V V
Max.
16
Unit
MHz
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Page 3
Electrooptical Characteristics (Note 1)
ILX553A
Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)
Item Min. Sensitivity Sensitivity nonuniformity Saturation output voltage Saturation exposure Dark voltage average
Symbol R PRNU VSAT SER VDRK
11.8
—
1
— —
Typ.
14.8 4 2
0.14
0.3
Max.
17.8 10
— —
2
Unit
V/(lx · s)
%
V
lx · s
mV
Remarks
Note 2 Note 3 Note 4 Note 5
Note 6
Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level
DSNU IL IVDD TTE ZO VOS
— — —
92
— —
0.6
0.02 15 98
230
6.2
3
—
30
— — —
mV
%
mA
%
Ω
V
Note 7
— — —
Note 8
Notes
1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D14, D15, to D62.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
PRNU = × 100 [%]
(VMAX – VMIN)/2
VAVE
The maximum output of 5150 pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE.
4) Use below the minimum value of the saturation output voltage.
5) Saturation exposure is defined as follows.
SE =
VSAT
R
6) Optical signal accumulated time τ int stands at 10ms.
7) VOUT = 500mV (Typ.)
8) VOS is defined as indicated bellow.
VOUT
VOS
GND
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Page 4
Clock Timing Chart 1
φ2
OUT
5 0
3
2
5 0
5
0 5 0
5 0
Note) The transfer pulses (φ1, φ2, φLH) must have more than 5220 cycles.
1
D1
4
D3
D2
Dummy signal (63 pixles)
D13
Optical black (49 pixles)
D15
D14
1-line output period (5220 pixles)
D61
D62
D63
S1
S2
S5148
S5149
S5150
D64
D65
φROG
φ1 φLH
φRS
– 4 –
φCLP
V
ILX553A
Page 5
Clock Timing Chart 2
ILX553A
φROG
φ1 φLH
φ2
Clock Timing Chart 3
φ1 φLH
t4
t2
t6 t7
t1
t7
t5
t3
t6
φ2
φRS
φCLP
OUT
V
t10
t9
t13
t16
t17
t11
t8
t14
t15
t12
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Page 6
Clock Timing Chart 4
Cross point φ1 and φ2
5V
φ1
ILX553A
0V
φ2
Cross point φLH and φ2
5V
φ2
0V
φLH
1.5V (Min.)
2.0V (Min.)
1.5V (Min.)
0.5V (Min.)
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Page 7
Clock Pulse Recommended Timing
ILX553A
Item
φROG, φ1 pulse timing φROG pulse high level per iod φROG, φ1 pulse timing φROG pulse rise time φROG pulse fall time φ1 pulse rise time/φ2 pulse fall time φ1 pulse fall time/φ2 pulse rise time φRS pulse high level period φRS, φCLP pulse timing φRS pulse rise time φRS pulse fall time φCLP pulse high level period φCLP, φLH pulse timing φCLP pulse rise time φCLP pulse fall time
Signal output delay time
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17
Min.
50
3 1 0 0 0
0 10 10
0
0 20
5
0
0
— —
Typ. 100
20
20 200 200
10
10 200
50
10
10
15
Max.
—
5 2 5 5
— —
10 10 60 60
1
∗
1
∗
— —
30 30
1
∗
1
∗
— —
30 30
—
8
—
Unit
ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1
∗
These timing is the recommended condition under fφRS = 1MHz.
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Page 8
Application Circuit
∗
IC2
φLH
φRS
φCLP
IC2
φROG
IC1
GND
GND
100Ω
φLH
100Ω
φRS
GND
100Ω
171819202122
100Ωφ22Ω
1213141516
φ2
φCLP
φROG
GND
GND
GND
– 8 –
GND
GND
GND
GND
OUT
V
1 2 3 4 5 6
DD
V
GND
φ1
GND
GND
7 8 9 10 11
GND
12V
∗
Data rate fφ
RS = 1MHz
100Ω
5.1kΩ
Tr1
2Ω
47µF/16V
IC1
V
OUT
IC1: 74AC04
φ1
IC2: 74HC04
0.1µF
Tr1: 2SC2785
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
ILX553A
Page 9
Example of Representative Characteristics (VDD = 12V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
Relative sensitivity
0.3
0.2
0.1 0
400 500 600 700
Wavelength [nm]
Dark signal output temperature characteristics
(Standard characteristics)
800
Integration time output voltage characteristics
ILX553A
900 1000
(Standard characteristics)
10
5
1
0.5
Output voltage rate
0.1 01020
Ta – Ambient temperature [˚C]
Offset level vs. VDD characteristics
(Standard characteristics)
10
8
6
30 40 50 60
Ta = 25˚C
1
0.5
Output voltage rate
0.1 1
τ int – integration time [ms]
510
Offset level vs. Temperature characteristics
(Standard characteristics)
10
8
6
∆V
∆Ta
OS
≈ –2mV/˚C
– Offset level [V]
OS
V
4
2
0
11.4
OS
∆V
≈ 0.6
∆V
DD
12.0 12.6
DD
[V]
– 9 –
– Offset level [V]
OS
V
4
2
0
0
Ta – Ambient temperature [˚C]V
302010 40 50 60
Page 10
Notes of Handling
1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive
shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Packages The following points should be observed when handling and installing packages.
a) Remain within the following limits when applying static load to the package:
(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter
of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm
ILX553A
Cover glass
Plastic portion
Ceramic portion
(1)
39N
Adhesive
29N
(2)
(3)
29N
(4)
0.9Nm
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the package to crack or dust to be generated.
(1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Pr ying the plastic portion and ceramic portion away at a support point of the adhesive layer. (5) Applying the metal a crash or a rub against the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.
d) The notch of the plastic portion is used for directional index, and that can not be used for reference of
fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap with the notch of the plastic portion.
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Page 11
3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to
scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
ILX553A
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Page 12
Package Outline Unit: mm
22 pin DIP (400mil)
55.7 ± 0.3
10.6 ± 0.3 22
36.05 (7µm X 5150pixels) 12
0˚ to 9˚
5.0 ± 0.3
V
H
No.1 Pixel
1
∗
53.00 or 54.2
11
7.3 or 9.0
10.0 ± 0.3
∗
10.16
0.25
– 12 –
4.0 ± 0.5
3.58
2.54
0.3
M
0.51
4.28 ± 0.5
1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
∗
The dimension of cover glass is 54.2 × 9.0mm or 53.0 × 7.3mm.
PACKAGE STRUCTURE
Sony Corporation
PACKAGE MATERIAL LEAD TREA TMENT LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
Plastic, Ceramic GOLD PLATING 42 ALLOY
5.43g LS-B23-01(E)
ILX553A
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