Datasheet ILX551A Datasheet (Sony)

Page 1

2048-pixel CCD Linear Sensor (B/W)

Description

The ILX551A is a reduction type CCD linear sensor designed for facsimile, image scanner and OCR use. This sensor reads B4 size documents at a density of 200DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use.

Features

• Number of effective pixels: 2048 pixels

• Pixel size: 14µm × 14µm (14µm pitch)

• Built-in timing generator and clock-drivers

• Ultra low lag

• Maximum clock frequency: 5MHz

Absolute Maximum Ratings

• Supply voltage VDD1 11 V

VDD2 6V

•Operating temperature –10 to +55 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

Block Diagram

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E00439-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

ILX551A

22 pin DIP (Cer-DIP)

22 20 17 16 15 14 13 12 10

91142119587632

VOUT

Output amplifier

Sample-and-hold

circuit

DD2

NC V

DD1 GND NC NC NC NC GND NC

DD2φROG

SHSWV

DD2

GND

φCLK

DD2NCNC

Clock pulse generator

Sample-and-hold pulse generator

Mode

selector

Read out gate

pulse generator

Clock-drivers

CCD analog shift register

Read out gate

D14

D15

D33

S2047

S2048

D34

D35

D36

D37

D38

D39

1 22

OUT

SHSW

φCLK

DD2

φROG

DD2

VDD2

VDD1

GND

2048

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ILX551A

Unit

pF pF

Max.

— —

Typ.

10 10

Min.

— —

Symbol CφCLK CφROG

Item Input capacity of φCLK pin Input capacity of φROG pin

Input Capacity of Pins

Item

Unit

V V

Max.

9.5

5.25

Typ.

9.0

5.0

Min.

8.5

4.75

Item VDD1 VDD2

Recommended Supply Voltage

Pin condition

Pin 4 SHSW

GND

VDD2

Mode in use

S/H Yes

Mode Description

Unit

V V

Max.

5.5

0.5

Typ.

5.0 —

Min.

4.5

0.0

Input clock high level Input clock low level

Recommended Input Pulse Voltage

Pin Description

Pin No.

Symbol Description

1 2 3

4 5

6 7 8

9 10 11

VOUT NC NC

SHSW φCLK

NC NC VDD2 VDD2 NC φROG

Signal output NC NC

with S/H → GND

Switch

without S/H → VDD2 Clock pulse NC NC 5V power supply 5V power supply NC Clock pulse

No.

Symbol Description

12 13 14

15 16

17 18 19 20 21 22

GND NC NC

NC NC

GND NC GND VDD1 VDD2 VDD2

GND NC NC

NC NC

GND NC GND 9V power supply 5V power supply 5V power supply

Note) Rules for raising and lowering power supply voltage

To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

{

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ILX551A

Unit Remarks

Max.

8.0 —

2.0

3.0 — — —

8.0

5.0 — — —

Typ.

2.0

1.8

0.3

0.5

0.02

6000

0.045

4.0

1.8

97.0 600

4.0

Min.

30 —

1.5 — — — — — — —

92.0 — —

Symbol R PRNU VSAT VDRK DSNU IL DR SE IVDD1 IVDD2 TTE ZO VOS

Item

Electrooptical Characteristics

(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm))

Notes)

1. For the sensitivity test light is applied with a uniform intensity of illumination.

2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = × 100 [%]

The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE.

3. Integration time is 10ms.

4. VOUT = 500mV

5. DR =

When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time.

6. SE =

7. Vos is defined as indicated below.

(VMAX – VMIN)/2

VAVE

VSAT

GND

D31 D32 D33 S1



,

V/(lx · s)

V mV mV

% —

lx · s

mA mA

Ω

Note 1 Note 2

— Note 3 Note 3 Note 4 Note 5 Note 6

—

— Note 7

Secsitivity Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level

VSAT

VDRK

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ILX551A

Fig. 1. Clock Timing Diagram (without S/H mode)

Dummy signal (33 pixels)

Optical black

(18 pixels)

Dummy signal

(6 pixels)

Effective picture

elements signal

(2048 pixels)

1-line output period (2087 pixels)

D11

D12

D13

D14

D15

D31

D32

D33

S2045

S2046

S2047

S2048

D34

D35

D36

S37

S38

D39

2087

φROG

φCLK

OUT

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ILX551A

Fig. 2. φCLK, VOUT Timing









φCLK

t3 t4

t2t1

OUT

Item

φCLK pulse rise/fall time φCLK pulse duty

∗1

φCLK – VOUT 1 φCLK – VOUT 2

Symbol t1, t2 — t5 t6

Min.

0 40 50 30

Typ.

10 50 80 75

Max.

—

60 110 120

Unit

% ns ns

∗1

100 × t3/(t3 + t4)

Fig. 3. φROG, φCLK Timing

φROG

φCLK

t7 t11

t8 t10t9

Item

φROG, φCLK pulse timing φROG pulse rise/fall time φROG pulse period

Symbol t7, t11 t8, t10 t9

Min.

500

Typ.

1000

Max.

— — —

Unit

ns ns ns

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ILX551A

Example of Representative Characteristics

Dark signal voltage rate vs. Ambient temperature

(Standard characteristics)

Dark signal voltage rate

0.5

0.1 0 10 20 30

Ta – Ambient temperature [°C]

40 50 60

VDD1, VDD2 supply current vs. Clock frequency

(Standard characteristics)

IVDD1

Ta = 25°C

VDD2

IVDD1, IVDD2 – VDD1, VDD2 supply current [mA]

0.5

0.1

0.1M 1M Clock frequency [Hz]

Spectral sensitivity characteristics

(Standard characteristics)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1 0

Relative sensitivity

400 500 600 700 800 900 1000

Wavelength [nm]

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ILX551A

Application Circuit

VOUT

SHSW

φCLK

DD2 (D)

φROG

VDD2 (D)

DD2 (D)

1Ω

0.01µ

10µ/16V

2SA1175

φCLK φROG

22µ/10V0.01µ

Output signal

3kΩ

VDD1 (A)

GND (A)

GND (D)

22 21 20 19 18 17 16 15 14 13 12

1 2 3 4 5 6 7 8 9 10 11

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

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ILX551A

Notes of Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.

2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package:

(1) Compressive strength: 39N/surface

(Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic

layers are shielded by low-melting glass,

(1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as

tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.

Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded

30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering

tool, ground the controller. For the control system, use a zero cross type.

Upper ceramic layer

39N

Lower ceramic layer

Low-melting glass

(1)

29N

(3)

0.9Nm

(4)

29N

(2)

Page 9

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ILX551A

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

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ILX551A

Package Outline Unit: mm

1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm.

2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.

7.35 ± 0.5

28.672 (14µm X 2048Pixels)

41.6 ± 0.5

No.1 Pixel

5.0 ± 0.5

4.0 ± 0.5

2.54 0.51

3.65

4.35 ± 0.5

0.25

0° to 9°

10.0 ± 0.5

0.3

22pin DIP (400mil)

Cer-DIP

TIN PLATING

42 ALLOY

5.20g

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

DRAWING NUMBER

LS-A18-01(E)

Sony Corporation