Datasheet ILX533K Datasheet (Sony)

2700 pixel × 3 line CCD Linear Sensor (Color)

For the availability of this product, please contact the sales office.

Description

The ILX533K is a reduction type CCD linear sensor
developed for color image scanner. The distance
between lines is only 4 line (32µm). This sensor reads
A4-size documents at a density of 300DPI.

Features

• Number of effective pixels: 8100 pixels

(2700 pixels × 3)

• Pixel size: 8µm × 8µm (8µm pitch)

• Distance between line: 32µm (4 Lines)

• Number of output 3 (R, G, B)

• Single-sided readout

• Clamp circuit are on-chip

• Ultra high sensitivity/Ultra low lag

• Single 12V power supply

• Maximum data rate: 9MHz (3MHz × 3)

• Input Clock Pulse: CMOS 5V drive

• Package: 22 pin cer-DIP (400 mil)

Block Diagram

φROG-B

11

ILX533K

22 pin DIP (Cer-DIP)

φROG-G
12

φROG-R
13

Absolute Maximum Ratings

• Supply voltage VDD 15 V

• Operating temperature –10 to +55 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

19

18

17

16

15

14

22

21

20

GND

GND

OUT-B

V

NC

NC

NC

NC

NC

φ2

φRS

OUT-R

V

VOUT-G

VDD

NC

NC

NC

NC

NC

1

2

3

4

5

6

7

8

9

Driver

φ2

14

S2700

Blue

Read Out Gate

S1
D63

D15
D14

CCD Register

VDD

4

Clamp

20

Green

S1

D63

D15
D14

Driver

S2700

Red

Read Out Gate

CCD Register

Clamp

3

S1

D63

D15
D14

Driver

S2700

Read Out Gate

CCD Register

Clamp Pulse

Clamp

2

Driver

Generator

10

1

21

φRS φ1

GND

φROG

φ1

10

11

-B

2700 G 1

2700 R 1

13

2700 B 1

12

φROG

φROG-G

-R

VOUT-B

VOUT-G

VOUT-R

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E97406B79-PS

Pin Description

Pin No. Symbol Description Pin No. Symbol Description

ILX533K

1
2
3
4
5
6
7
8

9
10
11

φRS
VOUT-R
VOUT-G
VDD
NC
NC
NC
NC
NC

φ1
φROG-B

Clock pulse input
Signal out (red)
Signal out (green)
12V power supply
NC
NC
NC
NC
NC
Clock pulse input
Clock pulse input

Recommended Supply Voltage

Item

VDD

Min.

11.4

Typ.

12

Max.

12.6

Unit

V

12
13
14
15
16
17
18
19
20
21
22

φROG-G
φROG-R
φ2

NC
NC
NC
NC
NC
VOUT-B
GND
GND

Clock pulse input
Clock pulse input
Clock pulse input
NC
NC
NC
NC
NC
Signal out (blue)
GND
GND

Clock Characteristics

Item
Input capacity of φ1, φ2
Input capacity of φRS
Input capacity of φROG

∗1

It indicates that φROG-R, φROG-G, φROG-B as φROG.

∗1

Symbol
Cφ1, Cφ2
CφRS
CφROG

Clock Frequency

Item Symbol

φ1, φ2, φRS fφ1, fφ2, fφRS

Input Clock Pulse Voltage Condition

Item

φ1, φ2, φRS, φROG
pulse voltage

High level
Low level

Min.

—
—
—

Min.

4.75
—

Min.

—

Typ.

400

10
10

Typ.

5.0
0

Typ.

1

Max.

—
—
—

Max.

5.25

0.1

Max.

3

Unit

pF
pF
pF

Unit

MHz

Unit

V
V

– 2 –

Electrooptical Characteristics (Note 1)

Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p,
Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)

Item Symbol Min. Typ. Max. Unit Remarks

ILX533K

Red

Sensitivity

Green

Blue
Sensitivity nonuniformity
Saturation output voltage

Red
Saturation
exposure

Green

Blue
Dark voltage average
Dark signal nonuniformity
Image lag
Supply current
Total transfer efficiency
Output impedance
Offset level

RR
RG
RB
PRNU
VSAT
SER
SEG
SEB
VDRK
DSNU
IL
IVDD
TTE
ZO
VOS

6.2

12.3

7.5
—

2.0

0.15

0.10

0.12
—
—
—
—
92
—
—

9.5
19

11.5
4

2.5

0.26

0.13

0.21
2
4

0.02

30
98

300

6.3

12.8

25.6

15.5
20
—
—
—
—

5
12
—
50
—
—
—

V/(lx · s)

%

V

lx · s

mV
mV

%

mA

%

Ω

V

Note 2

Note 3
Note 4

Note 5

Note 6
Note 6
Note 7

—
—
—

Note 8

Note

1) In accordance with the given electrooptical characteristics, the black level is defined as the average value
of D2, D3 to D12.

2) For the sensitivity test light is applied with a uniform intensity of illumination.

3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.

VOUT-G = 500mV (Typ.)
PRNU = × 100 [%]

(VMAX – VMIN) /2

VAVE

Where the 2700 pixels are divided into blocks of 100. The maximum output of each block is set to VMAX,
the minimum output to VMIN and the average output to VAVE.

4) Use below the minimum value of the saturation output voltage.

5) Saturation exposure is defined as follows.

SE =

VSAT

R

Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB.

6) Optical signal accumulated time τint stands at 5ms.

7) VOUT-G = 500mV (Typ.)

VOUT

8) Vos is defined as the right side.
VOUT indicates VOUT-R, VOUT-G, and VOUT-B.

– 3 –

VOS

GND

ILX533K

2770

D70

D65
D64

S2700
S2699
S2698

S2

S1

D63
D62
D61

D15
D14

Optical black (49 pixels)

D13

1-line output period

Clock Timing Chart 1

5

0

φROG

4
3
2

1

5

0

5

0

5

0

φ1

φ2

φRS

D3
D2

D1

OUT

V

Dummy signal (63 pixels)

Noto) The transfer pulses (φ1, φ2) must have more than 2770 cycles.

VOUT indicates VOUT-R, VOUT-G, VOUT-B.

– 4 –

Clock Timing Chart 2

φROG

ILX533K

t4 t5

t2

t7t6

φ1

φ2

Clock Timing Chart 3

φ1

φ2

t1 t3

t7

t9

t6

t14

t10 t11

φRS

OUT

V

t8

t13

t12

– 5 –

Clock Pulse Recommended Timing

ILX533K

Item

φROG, φ1 pulse timing
φROG pulse high level period
φROG, φ1 pulse timing
φROG pulse rise time
φROG pulse fall time
φ1 pulse rise time/φ2 pulse fall time
φ1 pulse fall time/φ2 pulse rise time
φRS pulse high level period
φRS, φ1 pulse timing 1
φRS pulse rise time
φRS pulse fall time

Signal output delay time

φRS, φ1/φ2 pulse timing 2

∗1

These timing is the recommended condition under fφRS = 1MHz.

Symbol

t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13

t14

Min.

50
800
800

0
0
0

0
50
80

0

0
—
—

50

Typ.

100
1000
1000

5

5
20
20

250
250

10
10
70
10

250

∗1

∗1
∗1

Max.

—
—
—
10
10
60
60
—
—
30
30
—
—

—

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

– 6 –

IC1: 74AC04

Tr1: 2SC2785

ILX533K

-R φROG-G

φ2 φROG

5.1kΩ

IC1

OUT-B

V

Tr1

IC1

-Bφ1

φROG

12

13

-B

φROG

-G

φROG

-R

φROG

φ1

11

10

2Ω

1415

φ2

NC

9

2Ω

NC

NC

16

NC

17

NC

18

NC

19

V

OUT-B

20

100Ω

GND

21

NC

NC

NC

NC

V

DD

V

OUT-G

OUT-R

V

8

7

6

5

4

100Ω

VOUT-G

5.1kΩ

3

Tr1

2

Tr1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

∗

Application Circuit

12V

22

0.1µF 47µF/16V

GND

– 7 –

φRS

1

100Ω

OUT-R

V

φRS

IC1

RS = 1MHz

Data rate fφ

∗

5.1kΩ

Example of Representative Characteristics (VDD = 12V, Ta = 25°C)

Spectral sensitivity characteristics (Standard characteristics)

1

0.8

0.6

0.4

Relative sensitivity

0.2

0

400 450 500 550 600 650 700

Wavelength [nm]

ILX533K

Dark signal output temperature characteristics

(Standard characteristics)

10

5

1

0.5

Output voltage rate

0.1
10 20 30 40 50 60 1

0

Ta – Ambient temperature [°C]

Offset level vs. VDD characteristics

(Standard characteristics)

12

Ta = 25°C

10

Integration time output voltage characteristics

(Standard characteristics)

1

0.5

Output voltage rate

0.1
510

τ int – Integration time [ms]

Offset level vs. temperature characteristics

(Standard characteristics)

12

10

8

6

– Offset level [V]

4

OS

V

2

0

11.4 12.6
V

12

DD [V]

∆V

OS

∆VDD

0.6
– Offset level [V]

OS

V

– 8 –

8

6

∆VOS

4

2

0

0

10 20 30 40 50 60

Ta – Ambient temperature [°C]

∆Ta

+0.5mV/°C

Notes of Handling

1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material.

Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.

2) Notes on Handling CCD Cer-DIP Packages
The following points should be observed when handling and installing cer-DIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:

(1)Compressive strength:39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of

the glass portion.)
(2)Shearing strength: 29N/surface
(3)Tensile strength: 29N/surface
(4)Torsional strength: 0.9Nm

ILX533K

Upper ceramic layer

lower ceramic layer

39N

Low-melting glass

(1)

29N 29N 0.9Nm

(2) (3) (4)

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic

layers are shielded by low-melting glass,
(1)Applying repetitive bending stress to the external leads.
(2)Applying heat to the external leads for an extended period of time with soldering iron.
(3)Rapid cooling or heating.
(4)Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as

tweezers.
(5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass.

Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.

3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W

soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an imaging device, do not use a solder suction equipment. When using an electric

desoldering tool, ground the controller. For the control system, use a zero cross type.

– 9 –

ILX533K

4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 10 –

0° to 9°

ILX533K

0.25

12

22pin DIP (400mil)

32.0 ± 0.5

21.6 (8µm × 2700Pixels)

(AT STAND OFF)

10.16

10.0 ± 0.5

9.0

11

No.1 Pixel (Green)

30.6

1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.

2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.

M

3.4 ± 0.5

0.3

2.7

0.51

Cer-DIP

42 ALLOY

TIN PLATING

3.0g

2.54

Package Outline Unit: mm

5.8 ± 0.8

22

H

V

1

5.0 ± 0.5

4.0 ± 0.5

PACKAGE MATERIAL

PACKAGE STRUCTURE

LEAD TREATMENT

PACKAGE WEIGHT

LEAD MATERIAL

– 11 –