Datasheet ILX532A Datasheet (Sony)

Page 1

7500-pixel CCD Linear Sensor (B/W)



Description

The ILX532A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600DPI, at high speed.

Features

• Number of effective pixels: 7500 pixels

• Pixel size: 7µm × 7µm (7µm pitch)

• Clamp circuit are on-chip

• Signal output phase of two-output

simultaneous-output (alternate-output is available)

• Ultra high sensitivity/Ultra low lag

• Max Data Rate: 40MHz

• Single 12V power supply

• Input Clock Pulse: CMOS 5V drive

• Package: 28 pin Cer-DIP (400mil)

ILX532A

28 pin DIP (Cer-DIP)

Block Diagram

Absolute Maximum Ratings

• Supply voltage VDD 15 V

• Operating temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

ODD

GND

VGG

NC NC

VDD

NC NC

10 11 12 13 14

1 2

3 4 5 6 7 8 9

28 27 26 25 24 23 22 21 20 19 18 17

7500

16 15

EVEN

φCLP- φRS-EVEN φLH-EVEN

VDD VOUT-EVEN VDD

NC NC

φ2-EVEN GND

EVEN

φ1VDD GND NC

φCLP-

φRS-ODD

φLH-ODD

OUT-ODD

φ2-ODD φ1-ODD

φROG

GND

VDD

EVEN

φ1-

φ2-EVEN

VDD

φLH-EVEN

φRS-EVEN

EVEN

φCLP-

D94

1718

D75

S7500 S7499

2627

28

CCD analog shift register

Output amplifier

VOUT-EVEN

Read out gate

D74

D26 D25

VGG

Read out gate

φROG pulse

generator

CCD analog shift register

Output amplifier

OUT-ODD

φROG

VDD

φ1-ODD

φ2-ODD

GND

φLH-ODD

2 34

φRS-ODD

ODD

φCLP-

GND

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E98344-PS

Page 2

Pin Description

ILX532A

No.

Symbol Description

1 2 3 4 5 6 7 8 9

φCLP-ODD φRS-ODD φLH-ODD

GND VOUT-ODD VGG NC NC

φ2-ODD φ1-ODD

VDD φROG NC NC

Clock pulse input (odd pixel) Clock pulse input (odd pixel) Clock pulse input (odd pixel) GND Signal out (odd pixel) Output circuit gate bias NC NC Clock pulse input (odd pixel) Clock pulse input (odd pixel) 12V power supply Readout gate clock pulse input NC NC

Recommended Supply Voltage

Pin No.

15 16 17 18 19 20 21 22 23 24 25 26 27 28

Symbol Description

NC GND VDD φ1-EVEN GND φ2-EVEN NC NC VDD VOUT-EVEN VDD

φLH-EVEN φRS-EVEN φCLP-EVEN

NC GND 12V power supply Clock pulse input (even pixel) GND Clock pulse input (even pixel) NC NC 12V power supply Signal out (even pixel) 12V power supply Clock pulse input (even pixel) Clock pulse input (even pixel) Clock pulse input (even pixel)

Unit

VDD

Item

Min.

11.4

Typ.

Max.

12.6

Clock Characteristics

Item Input capacity of φ1∗1, φ2 Input capacity of φLH Input capacity of φRS Input capacity of φCLP

∗1

Input capacity of φROG

∗1

It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD,

Symbol Cφ1, Cφ2 CφLH CφRS CφCLP CφROG

Min.

— — — — —

Typ.

500

10 10 10 10

φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP.

Clock Frequency

Typ.

1 2

φ1, φ2, φLH, φRS, φCLP Data rate

Symbol fφ1, fφ2, fφLH, fφRS, fφCLP fφR

Min.

— —

Max.

— — — — —

Max.

20 40

Unit

pF pF pF pF pF

Unit MHz MHz

Input Clock Pulse Voltage Condition

φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage

Low level High level

– 2 –

Min.

—

4.75

Typ.

5.0

Max.

0.1

5.25

Unit

V V

Page 3

ILX532A

Electrooptical Characteristics (Note 1)

(Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))

Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Register imbalance Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level

Notes)

1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23.

2. For the sensitivity test light is applied with a uniform intensity of illumination.

3. W lamp (2854K)

4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.

VOUT = 500mV (Typ.)

Symbol R1 R2 PRNU VSAT SE RI VDRK DSNU IL IVDD TTE Zo VOS

Min.

8.2 — —

1.8

0.13 — — — — — 92 — —

Typ.

25.1 4

2.5

0.23 1

0.3

0.6

0.02

30 98

150

6.5

Max.

13.8 — 10 — —

2.0

5.0 — 60 — — —

Unit V/(lx · s) V/(lx · s)

lx · s

% mV mV

% mA

Ω

Remarks

Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9

Note 10

— — —

Note 11

PRNU = × 100 [%]

The maximum output of each odd and even pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE.

5. Use below the minimum value of the saturation output voltage.

6. Saturation exposure is defined as follows. SE =

7. RI is defined as indicated bellow. VOUT = 500mV (Typ.) RI = × 100 [%]

Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE.

8. Optical signal accumulated time τ int stands at 10ms.

9. The difference between the maximum and average values of the dark output voltage is calculated for even

and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms.

10. VOUT = 500mV (Typ.)

11. VOS is defined as indicated below.

VOUT

(VMAX – VMIN)/2

VAVE

VSAT

| VODD-AVE – VEVEN-AVE |

VODD-AVE + VEVEN-AVE

()

VOS

GND

– 3 –

Page 4

ILX532A

3797

D93

D83

D81

D79

D77

D75

S7499

S7497

S7495

D73

D71

D69

D94

D84

D82

D80

D78

D76

S7500

S7498

S7496

D74

D72

D70

1-line output period (7594 pixels)

φROG

ODD

φ1-

φ1-EVEN

φLH-ODD

φLH-EVEN

ODD

φ2-

φ2-EVEN

ODD

φRS-

Clock Timing Chart 1 (simultaneous output)

φRS-EVEN

ODD

φCLP-

– 4 –

φCLP-EVEN

D27

D25

D23

OUT-ODD

D28

D26

D24

Optical black (48 pixels)

Dummy signal (74 pixels)

Note) The transfer pulses (φ1, φ2, φLH) must have more than 3797 cycles.

VOUT-EVEN

Page 5

Clock Timing Chart 2



ILX532A

t4 t5

φROG

φ1 φLH

φ2

Clock Timing Chart 3

φ1 φLH

φ2

φRS

t6 t7

t1 t3

t7 t6

t10 t11

φCLP

t13

OUT

Clock timing of φ1, φ2, φLH, φRS, φCLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output.

– 5 –

t14

t15

t12

t17t16

Page 6

Clock Timing Chart 4

Cross point φ1 and φ2

φ1

φ20V

Cross point φLH and φ2

φ2

ILX532A

1.5V (Min.) 1.5V (Min.)

φLH 0V

2.0V (Min.) 1.5V (Min.)

– 6 –

Page 7

ILX532A

3797

D93

D83 D81 D79 D77 D75 S7499 S7497 S7495

S3 S1

D73 D71

D69

D27 D25

D23

D94

D84 D82 D80 D78 D76 S7500 S7498 S7496

S4 S2

D74 D72

D70

D28 D26

D24

(48 pixels)

Optical black

1-line output period (7594 pixels)

φROG

3 2 1

φLH-ODD

ODD

φ2-

EVEN

φ1-

φLH-EVEN

ODD

φ1-

)

∗1

Clock Timing Chart 5 (alternate output

EVEN

φ2-

D5 D3

ODD

φRS-

ODD

φCLP-

VOUT-ODD

EVEN

φRS-

φCLP-

D6 D4

VOUT-EVEN

Dummy signal (74 pixels)

Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN, φCLP-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD, φCLP-ODD for half a cycle.

∗

Note) The transfer pulses (φ1, φ2, φLH) must have more than 3797 cycles.

– 7 –

Page 8

Clock Pulse Recommended Timing

ILX532A

Item

φROG, φ1 pulse timing φROG pulse high level period φROG, φ1 pulse timing φROG pulse rise time φROG pulse fall time φ1 pulse rise time/φ2 pulse fall time φ1 pulse fall time/φ2 pulse rise time φRS pulse high level period φRS, φCLP pulse timing φRS pulse rise time φRS pulse fall time φCLP pulse high level period φCLP, φLH pulse timing φCLP pulse rise time φCL pulse fall time

Signal output delay time

Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17

Min.

50 1000 1000

0 0 0

0 10 10

0 10

— —

Typ.

100 1500 1500

5 20 20

200 200

10 10

200

10 10

8 15

∗1

∗1 ∗1

∗1

Max.

— —

— 10 10 60 60

—

— 30 30

—

— 30 30

—

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

∗1

These timing is the recommended condition under fφ1 = 1MHz.

– 8 –

Page 9

1528 27 26

17 16

VDD

GND

EVEN

ILX532A

12V

0.1µF

IC1: 74AC04

Tr1: 2SC2785

13 14

16V

47µF

IC1

φROG

φ1-

VDD

GND

19 18

φ2-EVEN

21 20

VOUT-EVEN

Tr1

5.1kΩ

100Ω

22

24 23

25

VDD

VOUT-EVEN

VDD

φLH-EVEN

φRS-EVEN

φCLP-

EVEN

ODD

OUT-ODD

φ1-ODD

φ2-ODD

VGG

GND

φLH-ODD

φRS-ODD

φCLP-

10 11 12

4 5 6

φ1

2Ω

φ2

2Ω

Tr1

0.1µF

5.1kΩ

VOUT-ODD

IC1

100Ω

φRS φLH

φCLP

100Ω 100Ω

Data rate fφR = 2MHz.

∗1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Application Circuit

– 9 –

Page 10

Example of Representative Characteristics (VDD = 12V, Ta = 25°C)

Spectral sensitivity characteristics (Standard characteristics)

1.0

0.8

0.6

0.4

Relative sensitivity

0.2

ILX532A

500 600 1000

Dark signal output temperature characteristics

(Standard characteristics)

0.5

Output voltage rate

0.1 10 20 60

Ta – Ambient temperature [°C]

30 40 500

Offset level vs. VDD characteristics

(Standard characteristics)

Ta = 25°C

700 800 900400

Wavelength [nm]

Output voltage rate

Integration time output voltage characteristics

(Standard characteristics)

0.5

0.1 τ int – integration time [ms]

Offset level vs. Temperature characteristics

(Standard characteristics)

Vos – Offset level [V]

12.011.4

VDD [V]

∆Vos ∆V

0.6

12.6

– 10 –

Vos – Offset level [V]

10 20 60

Ta – Ambient temperature [°C]

∆Vos

∆Ta

30 40 500

–2mV/°C

Page 11

Notes of Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material.

Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.

2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package:

(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter

of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm

ILX532A

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

Upper ceramic layer 39N

Lower ceramic layer

(1)

Low-melting glass

29N

(2)

29N

(3)

c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic

layers are shielded by low-melting glass,

(1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as

tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass.

Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.

0.9Nm

(4)

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded

30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering

tool, ground the controller. For the control system, use a zero cross type.

– 11 –

Page 12

ILX532A

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 12 –

Page 13

ILX532A

0 to 9˚

1521

28pin DIP (400mil)

10.16 (AT STAND OFF)

10.0±0.5

9.0

0.25

3.60

0.46

4.40±0.5

2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.

1. The height from the bottom to the sensor surface is 2.4mm±0.3.

3. The notches of the package must not be used for reference of fixing.

Package Outline Unit: mm

71.00±0.8

52.5(7µmX7500pixels)

10.12±0.5

No. 1 Pixel

5.0±0.5

68.0

16.5 16.5

TIN PLATING

Cer-DIP

2.54

PACKAGE MATERIAL

4.0±0.5

PACKAGE STRUCTURE

LEAD TREATMENT

8.8g

42 ALLOY

LEAD MATERIAL

LS-C5(E)

PACKAGE MASS

DRAWING NUMBER

– 13 –