Datasheet ILX531A Datasheet (Sony)

Page 1

5150-pixel CCD Linear Sensor (B/W)

Description

The ILX531A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 400 DPI, and A4-size documents at a density of 600 DPI at high speed.

Features

• Number of effective pixels: 5150 pixels

• Pixel size: 7µm × 7µm (7µm pitch)

• Clamp circuit are on-chip

• Signal output phase of two-output

simultaneous-output

(alternate-output is available)

• Ultra high sensitivity/Ultra low lag

• Maximum data rate: 40MHz

• Single 12V power supply

• Input clock pulse: CMOS 5V drive

• Package:

22 pin Plastic DIP (400mil)

Absolute Maximum Ratings

• Supply voltage VDD 15 V

• Operating temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

Block Diagram

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E97X25B97-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

ILX531A

22 pin DIP (Plastic)

5150

2 3 4

5 6 7 8 9

φCLP-

ODD

GND

OUT-ODD

VGG

GND

φRS-ODD

φLH-ODD

φ2-ODD φ1-ODD

φROG

VOUT-EVEN VDD NC

GND

VDD

φCLP-EVEN φRS-EVEN

φLH-EVEN

φ2-EVEN

φ1-EVEN

D25

D26

D74

S5149

S5150

D75

D94

φROG pulse

generator

Read out gate

CCD analog shift register

φ1-ODD

φROG

φRS-ODD

φLH-

ODD

GND

φ2-

ODD

GND

φ1-EVEN

φ2-

EVEN

φLH-

EVEN

φRS-

EVEN

Read out gate

CCD analog shift register

OUT-ODD

VOUT-EVEN

VGG

φCLP-ODD

Output

amplifier

φCLP-EVEN

Output

amplifier

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ILX531A

Pin Description

Pin No. Symbol Description Pin No. Symbol Description

1 2 3 4 5 6 7 8

9 10 11

φCLP-ODD φRS-ODD φLH-ODD

GND VOUT-ODD VGG GND

φ2-ODD φ1-ODD

VDD φROG

Clock pulse input (odd pixel) Clock pulse input (odd pixel) Clock pulse input (odd pixel) GND Signal out (odd pixel) Output circuit gate bias GND Clock pulse input (odd pixel) Clock pulse input (odd pixel) 12V power supply Readout gate clock pulse input

12 13 14 15 16 17 18 19 20 21 22

VDD φ1-EVEN GND φ2-EVEN NC VDD VOUT-EVEN VDD

φLH-EVEN φRS-EVEN φCLP-EVEN

12V power supply Clock pulse input (even pixel) GND Clock pulse input (even pixel) NC 12V power supply Signal out (even pixel) 12V power supply Clock pulse input (even pixel) Clock pulse input (even pixel) Clock pulse input (even pixel)

Recommended Supply Voltage

Item

VDD

Min.

11.4

Typ.

Max.

12.6

Unit

Clock Characteristics

Symbol Cφ1, Cφ2 CφLH CφRS CφCLP CφROG

Min.

— — — — —

Typ.

400

10 10 10 10

Max.

— — — — —

Unit

pF pF pF pF pF

Item

Input capacity of φ1∗1, φ2

∗1

Input capacity of φLH

∗1

Input capacity of φRS

∗1

Input capacity of φCLP

∗1

Input capacity of φROG

Input Clock Pulse Voltage Condition

High level Low level

Min.

4.75 —

Typ.

5.0 0

Max.

5.25

0.1

Unit

V V

Item

φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage

∗1

It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD, φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP.

Clock Frequency

Min.

— —

Typ.

1 2

Max.

20 40

Unit MHz MHz

Item Symbol φ1, φ2, φLH, φRS, φCLP Data rate

fφ1, fφ2, fφLH, fφRS, fφCLP

fφR

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ILX531A

Electrooptical Characteristics (Note 1)

(Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))

Item Symbol Min. Typ. Max. Unit Remarks Sensitivity1 Sensitivity2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Register imbalance Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level

R1 R2 PRNU VSAT SE RI VDRK DSNU IL IVDD TTE ZO VOS

8.2 — —

1.8

0.13 — — — — —

— —

25.1 4

2.5

0.23 1

0.3

0.6

0.02

30 98

150

6.5

13.8 — 10 — —

2.0

5.0 — 60 — — —

V/(lx · s) V/(lx · s)

lx · s

% mV mV

% mA

Ω

Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9

Note 10

— — —

Note 11

Notes

1) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23.

2) For the sensitivity test light is applied with a uniform intensity of illumination.

3) W lamp (2854K)

4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.

VOUT = 500mV (Typ.) PRNU = × 100 [%]

Where the 5150 pixels are divided into blocks of even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.

5) Use below the minimum value of the saturation output voltage.

6) Saturation exposure is defined as follows. SE = VSAT/R1

7) RI is defined as indicated bellow. VOUT = 500mV (Typ.)

RI = × 100 [%]

Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE.

8) Optical signal accumulated time τ int stands at 10ms.

9) The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms.

(VMAX – VMIN) /2

VAVE

| VODD-AVE – VEVEN-AVE |

VODD-AVE + VEVEN-AVE

(

)

Page 4

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ILX531A

10) VOUT = 500 mV (Typ.)

11) VOS is defined as indicated bellow.

VOS

VOUT

GND

Page 5

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ILX531A

2622

φROG

φ1-

ODD

φ1-EVEN

φLH-ODD

φLH-EVEN

φ2-ODD

φ2-EVEN

φRS-ODD

φRS-EVEN

φCLP-ODD

φCLP-EVEN

VOUT-EVEN

VOUT-ODD

D23

D25

D27

D69

D71

D73

S5145

S5147

S5149

D75

D77

D79

D81

D83

D93

D24

D26

D28

D70

D72

D74

S5146

S5148

S5150

D76

D78

D80

D82

D84

D94

Optical black (48 pixels)

Dummy signal (74 pixels)

1-line output period (5244 pixels)

Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles.

Clock Timing Chart 1 (simultaneous output)

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ILX531A

Clock Timing Chart 2

φROG

φ1 φLH

φ2

Clock Timing Chart 3

φ1 φLH

φ2

φRS

φCLP

OUT

t7 t6

t10 t11

t14 t15

t12

t13

t16 t17

Clock timing of φ1, φ2, φLH, φRS, φCLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output.

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ILX531A

Clock Timing Chart 4

1.5V (Min.)

φ2 0V

φ1 5V

Cross point φ1 and φ2

2.0V (Min.) 0.5V (Min.)

φLH 0V

φ2 5V

Cross point φLH and φ2

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ILX531A

φROG

φ1-

ODD

φLH-ODD

φ2-

ODD

φ1-EVEN

φLH-EVEN

φ2-

EVEN

φRS-ODD

φRS-EVEN

VOUT-ODD

φCLP-

EVEN

VOUT-EVEN

Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles.

∗

Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN, φCLP-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD, φCLP-ODD for half a cycle.

2622

φCLP-ODD

D23

D25

D27

D69

D71

D73

S5145

S5147

S5149

D75

D77

D79

D81

D83

D93

D24

D26

D28

D70

D72

D74

S5146

S5148

S5150

D76

D78

D80

D82

D84

D94

Optical black (48 pixels)

Dummy signal (74 pixels)

1-line output period (5244 pixels)

Clock Timing Chart 5 (alternate output

∗

)

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ILX531A

Clock Pulse Recommended Timing

Symbol

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17

Min.

50 600 400

0 0 0

0 10 10

0 10

0 — —

Typ.

100 1000 1000

5 20 20

200

∗1

200

∗1

10 10

200

∗1

10 10

8 15

Max.

— — — 10 10 60 60 — — 30 30 — — 30 30 — —

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Item

φROG, φ1 pulse timing φROG pulse high level period φROG, φ1 pulse timing φROG pulse rise time φROG pulse fall time φ1 pulse rise time/φ2 pulse fall time φ1 pulse fall time/φ2 pulse rise time φRS pulse high level period φRS, φCLP pulse timing φRS pulse rise time φRS pulse fall time φCLP pulse high level period φCLP, φLH pulse timing φCLP pulse rise time φCLP pulse fall time

Signal output delay time

∗1

These timing is the recommended condition under fφ1 = 1MHz.

Page 10

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ILX531A

φCLP-

ODD

GND

OUT

ODD

GND

φRS-

ODD

φLH-

ODD

φ2-

ODD

φ1-

ODD

φROG

OUT

EVEN

GND

φCLP-

EVEN

φRS-

EVEN

φLH-

EVEN

φ2-

EVEN

φ1-

EVEN

100Ω

φCLP

100Ω

φRS

100Ω

φLH

IC1

100Ω

5.1kΩ

VOUT-ODD

φROG

IC1

2Ω

φ1

2Ω

φ2

12V

47µF/16V

0.1µF

IC1 : 74AC04

Tr1 : 2SC2785

VOUT-EVEN

5.1kΩ

100Ω

Tr1

0.1µF

Tr1

∗

Data rate fφR = 2MHz.

Application Circuit

∗

(simultaneous output)

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

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ILX531A

Example of Representative Characteristics

400 500 600 700 800 900 1000

Wavelength [nm]

0.2

0.4

0.6

0.8

1.0

Relative sensitivity

Spectral sensitivity characteristics (Standard characteristics)

Ta – Ambient temperature [°C]

0.1

Output voltage rate

Dark signal output temperature characteristics

(Standard characteristics)

0.5

10 20 30 40 50 60

τ int – integration time [ms]

0.1

Output voltage rate

Integration time output voltage characteristics

(Standard characteristics)

0.5

5 10

Ta – Ambient temperature [°C]

– Offset level [V]

Offset level vs. Temperature characteristics

(Standard characteristics)

10 20 30 40 50 60

∆VOS

∆Ta

–2mV/°C

∆VOS ∆VDD

0.6

Ta = 25°C

DD [V]

– Offset level [V]

Offset level vs. VDD characteristics

(Standard characteristics)

11.4 12.0 12.6

Page 12

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ILX531A

Notes of Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.

2) Notes on Handling CCD Packages The following points should be observed when handling and installing packages. a) Remain within the following limits when applying static load to the package:

(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter

of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the package to crack or dust to be generated.

(1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. (5) Applying the metal a crash or a rub against the plastic portion.

Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.

d) The notch of the plastic portion is used for directional index, and that can not be used for reference of

fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap with the notch of the plastic portion.

Plastic portion

Cover glass

39N

Ceramic portion

Adhesive

(1)

29N

(3)

0.9Nm

(4)

29N

(2)

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ILX531A

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded

30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering

tool, ground the controller. For the control system, use a zero cross type.

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

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ILX531A

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

DRAWING NUMBER

Plastic, Ceramic

GOLD PLATING

42ALLOY

LS-B20-01(E)

1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.

2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.

5.43g

11.12 ± 0.3

10.16

55.7 ± 0.3

2.54

0.51

0.25

7.3

53.0

3.58

22pin DIP(400mil)

36.05(7µmX5150pixels)

No.1 Pixel

10.0 ± 0.3

0˚to 9˚

4.28 ± 0.5

0.3

4.0 ± 0.5

5.0 ± 0.3

(AT STAND OFF)

Package Outline Unit: mm