Page 1
3000-pixel CCD Linear Image Sensor (B/W)
Description
The ILX526A is a rectangular reduction type CCD
linear image sensor designed for bar code POS
hand scanner and optical measuring equipment use.
A built-in timing generator and clock-drivers ensure
single 5V power supply for easy use.
Features
• Number of effective pixels: 3000 pixels
• Pixel size: 7µm × 200µm (7µm pitch)
• Single 5V power supply
• High sensitivity: 300V/(lx · s)
• Built-in timing generator and clock-drivers
• Built-in sample-and-hold circuit
• Electrical shutter function
• Clock frequency: 100kHz (Min), 1MHz (Max)
Absolute Maximum Ratings
• Supply voltage VDD 6V
•Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Internal Structure
8
9
13
14
ILX526A
22 pin DIP (Cer-DIP)
Readout gate pulse
generator
Shutter pulse
generator
D65
D56
S3000
S2999
Clock pulse
generator
7
φSHUTφROGφCLKT1S/HSW
6
2
Pin Configuration (Top View)
DD VDD GND VDD GND
22
Clock-drivers
1
Vgg
φCLK
2
NC
3
NC
4
5
NC
6
φROG
φSHUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
GND
V
DD
T1
NC
7
8
9
10
11
1
3000
22
21
20
19
18
17
16
15
14
13
12
V
DD
GND
V
OUT
NC
NC
NC
NC
NC
V
DD
GND
S/HSW
21
1
Vgg GND V
S3
Readout gate
S2
S1
D55
CCD analog shift register
D54
D25
D24
Output Amplifier
S/H circuit
Clock-drivers
Readout gate
CCD analog shift register
20
OUT
V
10
12
– 1 –
E97803-PS
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Pin Description
Pin No. Symbol Description
ILX526A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vgg
φCLK
NC
NC
NC
φROG
φSHUT
GND
VDD
T1
NC
S/HSW
GND
VDD
NC
NC
NC
Output circuit gate bias
Clock pulse input
NC
NC
NC
Readout gate pulse input
Electrical Shutter pulse input
GND
5V
TEST
NC
Switch (with S/H or without S/H)
GND
5V
NC
NC
NC
18
19
20
21
22
NC
NC
VOUT
GND
VDD
Mode Description
Mode in Use
With S/H
Without S/H
12 pin S/HSW
GND
VDD
Recommended Voltage
Item
VDD
Min.
4.5
Input Pin Capacity
Item
NC
NC
Signal output
GND
5V
Typ.
Max.
5.0
5.5
Symbol
Unit
V
Min.
Typ.
Max.
Unit
Input capacity of φCLK pin
Input capacity of φROG pin
Input capacity of φSHUT pin
CφCLK
CφROG
CφROG
—
—
—
– 2 –
10
10
10
—
—
—
pF
pF
pF
Page 3
Electro-optical Characteristics (Note 1)
Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K,
IR cut filter: CM-500S (t = 1.0mm), Without S/H mode
Item Symbol Min. Typ. Max. Unit Remarks
ILX526A
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
5V current consumption
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD
TTE
ZO
VOS
210
—
—
0.6
—
—
—
—
—
—
92.0
—
—
300
3700
5.0
0.8
2.5
5.0
5.0
320
0.003
7.0
97.0
250
2.5
390
—
10.0
—
6.0
12.0
—
—
—
17.0
—
—
—
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
%
Ω
V
Note 2
Note 3
Note 4
—
Note 5
Note 6
Note 7
Note 8
Note 9
—
—
—
Note 10
Note)
1. In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D24, D26 to D52. The odd black level is defined as the average value of D25 , D27 to D53.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. Light source: LED λ = 660nm
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
PRNU = × 100 [%]
(VMAX – VMIN)/2
VAVE
Where the 3000 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of
each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.
5. Integration time is 10ms.
6. The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. Integration time is 10ms.
7. Typical value is used for clock pulse and readout pulse. VOUT = 500mV.
8. DR =
VSAT
VDRK
When optical integration time is shorter, the dynamic range sets wider because dark voltage is in
proportion to optical integration time.
VSAT
9. SE =
R1
10. Vos is defined as indicated below.
VOUT
GND
D52 D53D51 D55 S1D54
VOS
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Page 4
D65
D64
D63
D62
D61
D60
D59
D58
D57
D56
S3000
S2999
S2998
S2997
(10 pixels)
Dummy signal
ILX526A
S4
S3
S2
S1
D55
D54
D53
D24
D23
D22
D21
D4
D3
2
1
0
–1
D2
D1
D0
Optical black
(3000 pixels)
elements signal
Effective picture
(30 pixels)
1-Line output period (3066 pixels)
Dummy signal (55 pixels)
0
5
φROG
Clock Timing Diagram (With S/H mode)
0
5
φSHUT
0
5
φCLK
OUT
V
3100 or more clock pulses are required.
– 4 –
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D65
D64
D63
D62
D61
D60
D59
D58
D57
D56
S3000
S2999
S2998
S2997
(10 pixels)
Dummy signal
ILX526A
S3
S2
S1
D55
D54
D53
D52
D24
D23
D22
D21
D4
2
1
0
–1
D3
D2
D1
D0
Optical black
(3000 pixels)
elements signal
Effective picture
(30 pixels)
1-Line output period (3066 pixels)
Dummy signal (55 pixels)
0
5
φROG
0
5
5
φSHUT
Clock Timing Diagram (Without S/H mode)
φCLK
0
– 5 –
OUT
V
3100 or more clock pulses are required.
Page 6
Input Clock Voltage Condition
VIH
Item
Min.
4.5
Typ.
VDD
Max.
5.5
Unit
V
∗
This is applied to the all external pulses.
(φCLK, φROG, φSHUT)
ILX526A
VIL
0.0
—
φCLK Timing (For all modes)
φCLK
Item
φCLK pulse rise/fall time
φCLK pulse Duty
∗1
100 × t4/ (t3 + t4)
∗1
0.1
t1 t2
V
t3 t4
Symbol
t1, t2
—
Min.
0
40
Typ.
10
50
Max.
100
60
Unit
ns
%
φROG, φCLK Timing
φROG
φCLK
φROG, φCLKpulse timing 1
φROG, φCLKpulse timing 2
φROG pulse rise/fall time
φROG pulse period
Item
t6 t8
t5 t9
t7
Symbol
t5
t9
(1/8) τ
(1/8) τ
t6, t8
t7
Min.
0
6τ
Typ.
(1/4) τ
(1/4) τ
10
10τ
Max.
(3/8) τ
(3/8) τ
100
20τ
Unit
ns
ns
ns
ns
Note) τ is the period of φCLK.
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φSHUT, φCLK Timing
φSHUT
ILX526A
φCLK
φ
SHUT pulse rise/fall time
φ
SHUT pulse period
φ
SHUT, φCLK pulse timing 1
φ
SHUT, φCLK pulse timing 2
φROG, φSHUT Timing
Item
t11 t13
t14 t15
t12
Symbol
t11, t13
t12
t14
t15
Min.
0
4000
150
150
Typ.
10
5000
200
200
Max.
100
—
250
250
Unit
ns
ns
ns
ns
φROG
φSHUT
Item
φROG, φSHUT pulse timing
t16 t17
Symbol
t16, t17
Min.
10τ
Typ.
—
Max.
—
Unit
ns
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Page 8
ILX526A
φCLK-VOUT Timing
φCLK
VOUT
VOUT
∗1
∗
2
t18
∗
3
t19
Item
Symbol
Min.
Typ.
Max.
Unit
φCLK-VOUT output delay time1
φCLK-VOUT output delay time2
∗1
fck = 500kHz, φCLK Duty = 50%, φCLK rise/fall time = 10ns
∗2
is data period
∗3
Using internal sample-and-hold circuit
Application Circuit (Without S/H mode (Note))
1
φROG
φSHUT
φCLK
2
3
4
5
6
7
8
9
10
11
Vgg
φCLK
NC
NC
NC
φROG
φSHUT
GND
V
DD
T1
NC
V
DD
GND
V
OUT
NC
NC
NC
NC
NC
V
DD
GND
S/HSW
t18
t19
22
21
20
19
18
17
16
15
14
13
12
0.01µ5V22µ/10V
—
—
3kΩ
2SA1175
230
210
—
—
ns
ns
Note) This circuit diagram is the case when internal S/H is not used.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 8 –
Page 9
Example of Representative Characteristics (VDD = 5V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
10
9
8
7
6
5
4
Relative sensitivity
3
2
1
ILX526A
0
400 500 600 700 800 900 1000
Wavelength [nm]
Dark signal output temperature characteristics (Standard characteristics)
10
5
1
0.5
Output voltage rate
0.1
0.05
0.01
–10 0 10 20 30 40 60
Ta – Ambient temperature [°C]
50
– 9 –
Page 10
ILX526A
Offset level vs. Temperature characteristics
(Standard characteristics)
5
4
3
2
– Offset level [V]
OS
V
1
0
0 102030405060
–10
∆VOS
∆Ta
Ta – Ambient temperature [°C]
–2.1mV/°C
Supply current vs. VDD characteristics
(Standard characteristics)
14
Ta = 25°C
12
Offset level vs. VDD characteristics
5
4
3
2
– Offset level [V]
OS
V
1
0
4.5
Output voltage vs. Integration time
10
(Standard characteristics)
Ta = 25°C
∆VOS
∆VDD
5 5.5
VDD [V]
(Standard characteristics)
0.49
10
8
6
– Supply current [mA]
4
VDD
I
2
0
4.5
5 5.5
VDD [V]
5
Output voltage rate
1
10
50 100
τ – Integration time [ms]
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Page 11
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-DIP Packages
The following points should be observed when handling and installing cer-DIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1)Compressive strength:39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of
the glass portion.)
(2)Shearing strength: 29N/surface
(3)Tensile strength: 29N/surface
(4)Torsional strength: 0.9Nm
ILX526A
Upper ceramic layer
Lower ceramic layer
39N
Low-melting glass
(1)
29N 29N 0.9Nm
(2) (3) (4)
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1)Applying repetitive bending stress to the external leads.
(2)Applying heat to the external leads for an extended period of time with soldering iron.
(3)Rapid cooling or heating.
(4)Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
– 11 –
Page 12
ILX526A
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch
the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
7) Normal output signal is not obtained immediately after device switch on.
– 12 –
Page 13
0° to 9°
ILX526A
0.25
12
22pin DIP (400mil)
32.0 ± 0.5
21.0 (7µm × 3000Pixels)
(AT STAND OFF)
10.16
10.0 ± 0.5
9.0
No.1 Pixel
11
30.6
1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.
2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.
M
3.4 ± 0.5
0.3
2.7
0.51
Cer-DIP
42 ALLOY
TIN PLATING
3.0g
2.54
Package Outline Unit: mm
5.5 ± 0.8
22
H
V
1
5.0 ± 0.5
4.0 ± 0.5
PACKAGE MATERIAL
LEAD TREATMENT
PACKAGE WEIGHT
LEAD MATERIAL
PACKAGE STRUCTURE
– 13 –
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