Datasheet ILX523A Datasheet (Sony)

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2700 pixel CCD Linear Sensor (B/W)

Description

The ILX523A is a reduction type CCD linear sensor designed for facsimile, scanner and OCR use. This sensor reads A3 size documents at a density of 200 DPI (Dot Per Inch).

In addition, this can be directly driven at 5V logic and operate on single 12V power supply for easy use.

ILX523A

22 pin DIP (Cer-DIP)

Features

• Number of effective pixels: 2700 pixels

• Pixel size: 11µm ×11µm (11µm pitch)

• Ultra low lag/High Sensitivity

• Built-in Feed through suppression circuit

• Built-in Sample-and-hold circuit

• Maximum data rate: 5MHz

• Single 12V power supply

Absolute Maximum Ratings

• Supply voltage VDD 15 V

• Operating temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

VOUT

φS/H

NC NC NC NC

φ1

φROG

10 11

2 3 4

5 6 7 8 9

2700

22 21 20 19 18 17 16 15 14 13 12

NC NC V

T1 φRS NC NC NC φ2 NC NC

Block Diagram

φRST1

Timing

D39

D34

S2700 S2699

S2 S1

D33

D15 D14

Generator

Timing

Generator

Read Out gate

CCD Analog Shift Register

• Output Amplifier

• Sample-and-Hold Circuit

• Feed Through Level

Clamp Circuit

VDD

GNDVOUT φROGφ1φ2

φS/H

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E97442A78

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Pin Description

Pin No. Symbol Description Pin No. Symbol Description

ILX523A

1 2 3 4 5 6 7 8

9 10 11

VOUT GND NC φS/H NC NC NC NC φ1 NC φROG

Signal output GND NC Sample-and-Hold pulse NC NC NC NC Transfer pulse 1 NC Read out gate pulse

12 13 14 15 16 17 18 19 20 21 22

NC NC φ2 NC NC NC φRS T1 VDD NC NC

Note) Connect Pin 4 to GND when not using internal sample-and-hold circuit.

Recommended Pin Voltage

Item

VDD

Min.

11.4

Typ.

12.0

Max.

12.6

Unit

NC NC Transfer pulse 2 NC NC NC Reset gate pulse Test pin (Open) 12V power supply NC NC

Clock Characteristics

Item Input capacitance of φ1 Input capacitance of φ2 Input capacitance of φROG Input capacitance of φRS Input capacitance of φS/H Data Rate

Symbol Cφ1 Cφ2 CφROG CφRS CφS/H

—

Min.

— — — — — —

Typ.

300 300

10 10 10

1.0

Max.

— — — — —

5.0

Unit

pF pF pF pF pF

MHz

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Electrooptical Characteristics

(Ta = 25°C, VDD = 12V, data rate = 1MHz, mode without S/H (Pin 4 = GND), light source = 3200K, IR cut filter CM-500S (t = 1.0mm) used)

Item Symbol Min. Typ. Max. Unit Remarks

ILX523A

Sensitivity Sencitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image Lag Dynamic range Saturation exposure Supply current Total transfer efficiency Output impedance Offset level

Notes)

1. For the sensitivity test, light is applied with a uniform intensity of illumination.

2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. The output signal amplitude for test is 1V.

PRNU = × 100 [%]

(VMAX – VMIN)/2

VAVE

R1 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS

66.5 —

2.0 — — — — — —

92.0 — —

2.0

2.5

2.0

7.0

0.02

1250

0.02

15.0

98.0 300

7.4

123.5

10.0 —

8.0

14.0 — — —

25.0 — — —

V/(lx · s)

V mV mV

% —

lx · s

Ω

Note 1 Note 2

— Note 3 Note 3 Note 4 Note 5 Note 6

—

— Note 7

The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE.

3. Optical signal accumulated time stands at 10ms.

4. Output signal amplitude VOUT = 500mV.

5. Dynamic range is defined as follows.

DR =

When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage.

6. Saturation exposure is defined as follows.

SE =

7. VOS is defined as indicated below.

VSAT VDRK

VSAT

VOUT

D30 D31D29 D33 S1D32

VOS

GND

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ILX523A

2739

D39 D38 D37 D36 D35 D34 S2700 S2699 S2698 S2697

S3 S2 S1

D33

D32 D31

D15 D14 D13 D12 D11

Dummy signal (6 pixels)

(2700 pixels)

Effective picture elements signal

(18 pixels)

Optical black

1-line output period (2739 pixels)

Note) 2750 or more clock pulses (φ1, φ2, φRS) are required.

234561 21

φROG

φ1

φ2

φRS

Clock Timing Diagram (without internal sample-and-hold circuit)

– 4 –

D6 D5 D4

Dummy signal (33 pixels)

OUT

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ILX523A

2739

D39

D38 D37 D36

D35 D34 S2700 S2699 S2698 S2697

S4 S3 S2 S1 D33 D32 D31

D15 D14 D13 D12 D11

Dummy signal (6 pixels)

(2700 pixels)

Effective picture elements signal

(18 pixels)

Optical black

1-line output period (2739 pixels)

Note) 2750 or more clock pulses (φ1, φ2, φRS, φS/H) are required.

234561 21

φROG

φ1

φ2

φRS

Clock Timing Diagram (using internal sample-and-hold circuit)

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φS/H

D6 D5 D4

D2 D1

Dummy signal (33 pixels)

OUT

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Input Clock Waveform Conditions

φ1, φ2, φRS, φS/H pulses related

φ1

ILX523A

t1 t2

90%

10%

φ2

φRS

φS/H

VOUT (without internal sample-and-hold circuit)

VOUT (using internal sample-and-hold circuit)

t13

10%

90%

10%

90%

10%

t8 t9

t12

t19

t6t5

50%

90%

10%

t11t10

50%

φROG, φ1 pulses related

φROG

φ1

50%

t17 t18

90%

50%

10%

t16

t14

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t15

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Cross point φ1 and φ2

φ1 5V

ILX523A

φ2 0V

Input Clock Waveform Conditions

Item

φ1, φ2 rise/fall time φRS pulse low level period φ1, φ2 – φRS pulse timing φRS rise/fall time φS/H pulse low level period φ1, φ2 – φS/H pulse timing φRS – φS/H pulse timing φS/H rise/fall time

Signal output delay time

2.0V (Min.) 2.0V (Min.)

Symbol t1, t2 t3 t4 t5, t6 t7 t8 t9 t10, t11 t12 t13

Min.

0 20 25

0 20 70 15

0 — —

Typ.

200

— 10 40 20

∗1

Max.

100 200 350

40 200 350

—

Unit

ns ns ns ns ns ns ns ns ns ns

φROG pulse high level period φ1 – φROG pulse timing φROG rise/fall time

High level

Inpuyt clock pulse voltage

Low level

∗1

Recommended conditions for data rate = 1MHz.

t19 t14 t15, t16 t17, t18

— 500 500

4.5 0

20 1000 1000

—

— — —

100

5.5

0.5

ns ns ns ns

V V

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ILX523A

12V

10µ/16V

0.01µ

φ2

φRS

OUT

φROG

φ1

φS/H

GND

10kΩ

Application Circuit

10µ/16V

0.01µ

74HC04

φRS

φS/H

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

2SC2785

Output signal

Connect Pin 4 to GND or φROG

when not using internal

φ1

φ2

φROG

sample-and-hold circuit.

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Example of Representative Characteristics (VDD = 12V, Ta = 25°C)

Spectral sensitivity characteristics (Standard characteristics)

Relative sensitivity

ILX523A

400 500 600 700 800 900 1000

Wavelength [nm]

Dark signal output temperature characteristics (standard characteristics)

100

0.5

Output voltage rate

0.1

0.05

0.01 –10 20 30 40 60

Ta – Ambient temperature [°C]

50010

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ILX523A

Offset level vs. Temperature characteristics

(Standard characteristics)

– Offset level [V]

–10 0 30 6040

Ta – Ambient temperature [°C]

∆Vos

∆Ta

10 20

–5mV/ °C

Supply current vs. VDD characteristics

(Standard characteristics)

Offset level vs. VDD characteristics

(Standard characteristics)

∆Vos

– Offset level [V]

11.4 11.6 12.2 12.612.4

11.8 12.0

∆VDD

VDD [V]

Output voltage vs. Integration time

(Standard characteristics)

0.8

– Supply current [mA]

11.4 11.6 12.2 12.612.4

11.8 12.0 VDD [V]

Output voltage rate

10 50 100

τ – Integration time [ms]

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Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material.

Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.

2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing Cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package:

(1)Compressive strength:39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of

the glass portion.) (2)Shearing strength: 29N/surface (3)Tensile strength: 29N/surface (4)Torsional strength: 0.9Nm

ILX523A

Upper ceramic layer

Lower ceramic layer

39N

Low-melting glass

(1)

29N 29N 0.9Nm

(2) (3) (4)

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic

layers are shielded by low-melting glass, (1)Applying repetitive bending stress to the external leads. (2)Applying heat to the external leads for an extended period of time with soldering iron. (3)Rapid cooling or heating. (4)Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as

tweezers. (5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass.

Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered.

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W

soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an imaging device, do not use a solder suction equipment. When using an electric

desoldering tool, ground the controller. For the control system, use a zero cross type.

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ILX523A

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch

the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

7) Normal output signal is not obtained immediately after device switch on.

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ILX523A

0° to 9°

22pin DIP (400mil)

0.25

10.16 (AT STAND OFF)

10.0 ± 0.5

9.0

1. The height from the bottom to the sensor surface is 2.45 ± 0.3mm.

2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.

4.45 ± 0.5

3.65

0.3

Package Outline Unit: mm

41.6 ± 0.5

29.7 (11µm × 2700Pixels)

6.73 ± 0.8

No.1 Pixel

5.0 ± 0.5

40.2

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2.54 0.51

42 ALLOY

TIN PLATING

Cer-DIP

5.2g

4.0 ± 0.5

PACKAGE MATERIAL

LEAD MATERIAL

LEAD TREATMENT

PACKAGE WEIGHT

PACKAGE STRUCTURE