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ILX521AA
256-pixel CCD Linear Image Sensor (B/W)
Description
The ILX521AA is a rectangular reduction type CCD
linear image sensor designed for image scanner
sensor. A built-in timing generator and clock driver
ensure single 5V power supply for easy use.
Features
• Number of effective pixels: 256 pixels
• Pixel size: 14µm × 14µm (14µm pitch)
• Built-in timing generator and clock driver
• Built-in S/H circuit
• Maximum data rate: 2MHz
• Single 5V power supply
• Clear mold package (20-pin SOP)
Absolute Maximum Ratings
• Supply voltage VDD 6V
•Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
Block Diagram
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E99155-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
20 pin SOP (MOLD)
7
8
9
10
14
13
12
11
20
19
18
17
16
15
1
2
3
4
5
6
NC
NC
GND
V
OUT
TEST
φCLK
S/H SW
φROG
NC
NC
NC
NC
NC
NC
NC
V
DD
NC
NC
NC
NC
1
256
TEST GNDVOUT VDD S/H SW
Readout gate
CCD analog shift register
Clock driver
Mode selector
ROG pulse
generator
Clock pulse generator
64 3 15 87
φROGφCLK
D7
D8
D12
S1
S2
S255
S256
D13
D17
5
• Output amplifier
• S/H circuit
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ILX521AA
Pin Description
Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
NC
NC
GND
VOUT
TEST
φCLK
S/H SW
φROG
NC
NC
NC
NC
GND
Signal output
Test (open)
Clock pulse input
Switching of with S/H or without S/H
Readout gate pulse input
NC
NC
Pin No. Symbol Description
11
12
13
14
15
16
17
18
19
20
NC
NC
NC
NC
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
5V power supply
NC
NC
NC
NC
NC
Input Pin Capacity
CφCLK
CφROG
Min.
—
—
Typ.
10
10
Max.
—
—
Unit
pF
pF
Item Symbol
Input capacity of φCLK pin
Input capacity of φROG pin
Input Clock Voltage Condition
∗1
High level
Low level
Min.
Symbol
4.5
0
VIH
VIL
Typ.
VDD
—
Max.
VDD + 0.5
0.5
Unit
V
V
Item
∗1
This is applied to the all external pulses. (φCLK, φROG)
Mode Description
Used mode
with S/H
without S/H
Pin 7 S/H SW
GND
VDD
Recommended Voltage
Item
VDD
Min.
4.75
Typ.
5.0
Max.
5.25
Unit
V
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ILX521AA
Electrooptical Characteristics
(Ta = 25°C, VDD = 5V, Data rate = 1MHz, Without S/H mode, Light source = 3200K,
IR cut filter CM-500S (t = 1mm))
Item Symbol Min. Typ. Max. Unit Remarks
Sensitivity
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
Current consumption
Total transfer efficiency
Output impedance
Offset level
R
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD
TTE
ZO
VOS
13.3
—
0.6
—
—
—
—
—
—
92.0
—
—
19.0
5.0
0.8
0.3
0.5
0.02
2666
0.042
5.0
98.0
350
3.8
24.7
12.0
—
2.0
3.0
—
—
—
12.0
—
—
—
V/(lx · s)
%
V
mV
mV
%
lx · s
mA
%
Ω
V
Note 1
Note 2
—
Note 3
Note 3
Note 4
Note 5
Note 6
—
—
—
Note 7
Note)
1. For the sensitivity test light is applied with a uniform intensity of illumination.
2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU = × 100 [%]
The maximum output of the 256 pixels is set to VMAX, the minimum output to VMIN and the average output to
VAVE.
3. Integration time is 10ms.
4. VOUT = 500mV.
5. DR = VSAT/VDRK
When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in
proportion to optical integration time.
6. SE = VSAT/R1
7. Vos is defined as indicated below.
(VMAX – VMIN)/2
VAVE
,
D8 D9 D10 D11 D12 S1
Vout
V
OS
GND
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ILX521AA
φROG
φCLK
VOUT
0V
5V
5V
0V
21 3 6 7 8 9 10 11 12 13 14
268
269
270
271
272
273
1
D1
D2
D3
D6
Optical black
(4 pixels)
Effective pixel
signal
(256 pixels)
Dummy signal
(5 pixels)
Dummy signal (12 pixels)
1-line output period (273 pixels)
Note) 280 or more clock pulses are required.
D7
D8
D9
D10
D11
D12
S1
S2
S256
D13
D14
D15
D16
D17
Clock Timing Diagram (without internal S/H mode)
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ILX521AA
210 3
φROG
φCLK
V
OUT
0V
5V
5V
0V
6 7 8 9 10 11 12 13 14 268
269
270
271
272
273
1
D0
D1
D2
D6
Optical black
(4 pixels)
Effective pixel
signal
(256 pixels)
Dummy signal
(5 pixels)
Dummy signal (13 pixels)
1-line output period (274 pixels)
Note) 280 or more clock pulses are required.
D7
D8
D9
D10
D11
D12
S1
S256
D13
D14
D15
D16
D17
Clock Timing Diagram (with internal S/H mode)
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ILX521AA
φCLK Timing (For all modes)
t1 t2
t3 t4
φCLK
90%
50%
10%
φROG, φCLK Timing
t6
t7
t8
φROG
φCLK
t5 t9
90%
90%
10%
Item Symbol Min. Typ. Max. Unit
φCLK pulse rise/fall time
φCLK pulse Duty
∗1
t1, t2
—
0
40
10
50
100
60
ns
%
∗
1
100 × t4/(t3 + t4)
Item Symbol Min. Typ. Max. Unit
φROG, φCLK pulse timing 1
φROG, φCLK pulse timing 2
φROG pulse rise/fall time
φROG pulse period
t5
t9
t6, t8
t7
500
500
0
500
1000
1000
10
1000
—
—
—
—
ns
ns
ns
ns
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ILX521AA
φCLK
VOUT
VOUT
∗
(Note 2)
t12
t11t10
(Note 3)
Item Symbol Min. Typ. Max. Unit
φCLK – VOUT output delay time 1
φCLK – VOUT output delay time 2
φCLK – VOUT∗(with S/H) output delay time
t10
t11
t12
—
—
—
150
220
110
—
—
—
ns
ns
ns
Note 1) fck = 1MHz, φCLK pulse Duty = 50%, φCLK pulse rise/fall time = 10ns
Note 2) Output waveform when internal S/H circuit is used.
Note 3) • is data period.
φCLK Output Signal Timing (Note 1)
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ILX521AA
φCLK φROG
TEST
φCLK
S/H SW
φROG
NC
NC
NC
5V
VDD
NC
NC
NC
NC
5 6 7 8
NC
NC
VSSVOUT
1 2 3 4 9 10
111213141516
NC
NC
NC
171819
NC
20
0.01µ
22µ/10V
3kΩ
2SA1175
Signal output
Note) This circuit diagram is the case when internal S/H mode is not used.
Connect Pin 7 to GND when internal S/H mode is used.
Application Circuit (without internal S/H mode)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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ILX521AA
Example of Representative Characteristics (VDD = 5V, Ta = 25°C)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400 500 600 700
Wavelength [nm]
Spectral sensitivity characteristics (Standard characteristics)
Relative sensitivity
800 900 1000
100
50
10
5
1
0.5
0.1
0.05
0.01
–10 0 10 20
Ta – Ambient temperature [°C]
Output voltage vs. Temperature characteristics (Standard characteristics)
Output voltage rate
30 40 50 60
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ILX521AA
5
4
7
6
3
2
1
0
–10
0 10 20
Ta – Ambient temperature [°C]
Offset level vs. Temperature characteristics
(Standard characteristics)
Vos – Offset level [V]
30 40 50 60
7
6
5
4
0
1
2
3
4.75
V
DD [V]
Offset level vs. VDD characteristics
(Standard characteristics)
Vos – Offset level [V]
5 5.25
∆Vos
∆V
DD
~
–
0.8
Ta = 25°C
10
8
7
5
9
6
4
2
3
1
0
4.75
5
V
DD [V]
Supply current vs. VDD characteristics
(Standard characteristics)
IVDD – Supply current [mA]
5.25
10
5
1
1
τ – Integration time [ms]
Output voltage vs. Integration time
(Standard characteristics)
Output voltage rate
5 10
∆Vos
∆Ta
~
–
–2mV/°C
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ILX521AA
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount,
cool sufficiently.
c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering
tool, ground the controller. For the temperature control system, use a zero-cross type.
3) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch mirror surfaces by hand or have any object come in contact with mirror surfaces.
Should dirt stick to a mirror surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the mirror surfaces are grease stained. Be careful not to
scratch the mirror surfaces.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation on the mirror surfaces,
preheat or precool when moving to a room with great temperature differences.
4) Do not expose to intense light for long periods.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
7) Normal output signal is not obtained immediately after device switch on.
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ILX521AA
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
1
10
1120
A
H
V
B
0.1
+0.2
- 0.1
0.8
0.15
+0.1
- 0.05
13.3 ± 0.3
11.6 ± 0.1
5.00 ± 0.4
0.8
0.3 ± 0.1
4.0 ± 0.1
6.9 ± 0.3
9.5 ± 0.3
2.4 ± 0.2
0.05 ± 0.04
DETAIL A
0.5 ± 0.2
0˚ to 10˚
DETAIL B
0.15
3.66 ± 0.4
Ø0.8 depth 0.05
1st.pin Index
15˚(All sides)
15˚(All sides)
M
0.15
Ø3.5 depth 0.05
(bottom)
Plastic
SOLDER PLATING
42ALLOY
0.31g
LS-F7(E)
20pin SOP
1. The height from the sensor surface is 1.55 ± 0.2mm.
2. The refractive index of the resin is 1.57.
Package Outline Unit: mm
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