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5150-pixel CCD Linear Sensor (B/W)
For the availability of this product, please contact the sales office.
Description
The ILX510 is a reduction type CCD linear sensor
developed for high resolution copiers. This sensor
reads A3-size documents at a density of 400 DPI,
and A4-size documents at a density of 600 DPI at
high speed.
Features
• Number of effective pixels: 5150 pixels
• Pixel size: 7 µm×7 µm (7 µm pitch)
• Signal output phase of two-output
simultaneous-output
(alternate-output is available)
• Ultra high sensitivity/Ultra low lag
• Max Data Rate: 40 MHz
• Single 12 V power supply
• Input Clock Pulse: CMOS 5V drive
• Package: 22 pin cer-DIP (400 mil)
Block Diagram
ILX510
20 pin DIP (Cer-DIP)
Absolute Maximum Ratings
• Supply voltage VDD 15 V
• Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (TOP VIEW)
22
21
20
19
18
17
16
15
14
13
GND
GND
V
OUT-EVEN
VDD
φRS-EVEN
φLH-EVEN
NC
NC
φ2-EVEN
φ1-EVEN
φROG
NC
1
VGG
2
V
OUT-ODD
3
VDD
4
φRS-ODD
5
φLH-ODD
6
NC
7
GND
8
φ2-ODD
9
φ1-ODD
10
VDD
11 12
1
5150
φRS-EVEN φLH-EVEN φ2-EVEN φ1-EVEN
GND VDD
fROG pulse
D94
1314171821 19
CCD analog shift register
Output amplifer
20
OUT-EVEN
V
Read out gate
22
GND
D75
S5150
S5149
S2
S1
D74
D26
D25
Read out gate
CCD analog shift register
2
VGG
generator
Output amplifer
3
VOUT-ODD
φROG
DD
V
10 11 12
φ1-ODD
φ2-ODD
GND
φLH-ODD φRS-ODD
4 5 6 8 9
VDD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94106-TE
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Pin Description
Pin No Symbol Description Pin No Symbol Description
1NCNC 12φROG Readout gate clock pulse input
2VGG Output circuit gate bias 13 φ1-EVEN Clock pulse input (even pixel)
3VOUT-ODD Signal out (odd pixel) 14 φ2-EVEN Clock pulse input (even pixel)
4VDD 12 V power supply 15 NC NC
5 φRS-ODD Clock pulse input (odd pixel) 16 NC NC
6 φLH-ODD Clock pulse input (odd pixel) 17 φLH-EVEN Clock pulse input (even pixel)
7NCNC 18φRS-EVEN Clock pulse input (even pixel)
8 GND GND 19 VDD 12 V power supply
9 φ2-ODD Clock pulse input (odd pixel) 20 VOUT-EVEN Signal out (even pixel)
10 φ1-ODD Clock pulse input (odd pixel) 21 GND GND
11 VDD 12 V power supply 22 GND GND
Recommended Supply Voltage
Item Min. Typ. Max. Unit
VDD 11.4 12 12.6 V
ILX510
Clock Characteristics
Item Symbol Min. Typ. Max. Unit
Input capacity of φ1∗, f2
Input capacity of φLH
Input capacity of φRS
∗
∗
∗
Cφ1, Cφ2 — 400 — pF
CφLH —10—pF
CφRS —10—pF
Input capacity of φROG CφROG —10—pF
∗
It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD, φRS-EVEN
as φRS.
Clock Frequency
Item Symbol Min. Typ. Max. Unit
φ1, φ2, φLH, φRS fφ1, fφ2,fφLH,fφRS — 1 20 MHz
Data rate fφR — 2 40 MHz
Input Clock Pulse Voltage Condition
Item Min. Typ. Max. Unit
φ1, φ2, φLH, φRS, φROG pulse voltage
High level 4.75 5.0 5.25 V
Low level — 0 0.1 V
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Electrooptical Characteristics (Note 1)
(Ta = 25 °C, VDD = 12 V, Data rate fφR=2 MHz, Simultaneous output, Input clock =5 Vp-p
Light source = 3200 K, IR cut filter CM-500S (t = 1.0 mm)
Item Symbol Min. Typ. Max. Unit Remarks
Sensitivity 1 R1 9 12 15 V/(lx•s) Note2
Sensitivity 2 R2 — 27.4 — V/(lx•s) Note3
Sensitivity nonuniformity PRNU — 4 10 % Note4
Saturation output voltage VSAT 1.0 1.5 — V Note5
Saturation exposure SE 0.067 0.125 — lx•s Note6
Register imbalance RI — 2 7 % Note7
Dark voltage average VDRK — 0.3 2.0 mV Note8
Dark signal nonuniformity DSNU — 0.6 3.0 mV Note9
Image lag IL — 0.02 — % Note10
Supply current IVDD —3060mA—
Total transfer efficiency TTE 92 98 — % —
Output impedance ZO — 150 — Ω —
Offset level VOS — 6.5 — V Note11
Dynamic range DR 500 5000 — — Note12
ILX510
Note
1) In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D6, D8 to D24. The odd black level is defined as the average value of D5, D7 to D23.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) W lamp (2854 K).
4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT=500 mV (Typ.)
PRNU =
Where the 5150 pixels are divided into blocks of 103, even and odd pixels, respectively. The maximum
output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.
5) Use below the minimum value of the saturation output voltage.
6) Saturation exposure is defined as follows.
(VMAX – VMIN)/2
VAVE
×100 (%)
SE =
VSAT
R1
7) RI is defined as indicated below. VOUT=500 mV (Typ.)
VODD-AVE – VEVEN-AVE
RI =
Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE.
VODD-AVE + VEVEN-AVE
(
2
×100 (%)
)
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ILX510
8) Optical signal accumulated time τ int stands at 10 ms.
9) The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectivery. The larger value is defined as the dark signal nonuniformity.
Optical signal accumulated time t int stands at 10 ms.
10) VOUT = 500 mV (Typ.)
11) Vos is defined as indicated bellow.
VOUT
VOS
GND
12) Dynamic range is defined as follows.
VSAT
DR =
VDRK
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical
signal accumulated time is in proportion to the dark voltage.
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ILX510
2622
D93
D83
D81
D79
D77
D75
S5149
S5147
S5145
S3
S1
D73
D71
D69
D94
D84
D82
D80
D78
D76
S5150
S5148
S5146
S4
S2
D74
D72
D70
1-line output period (5244 pixels)
D27
D25
D23
5
φROG
3
2
1
5
0
φLH-ODD
φLH-EVEN
5
φ2-ODD
0
EVEN
φ1-ODD
φ1-
0
φ2-EVEN
5
φRS-ODD
0
φRS-EVEN
D5
D3
D1
VOUT-ODD
Clock Timing Chart 1 (simultaneous output)
D28
D26
D24
D6
D4
D2
VOUT-EVEN
Optical black (48 pixels)
Dummy signal (74 pixels)
Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles.
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Clock Timing Chart 2
ILX510
φROG
φ1
φLH
φ2
Clock Timing Chart 3
φ1
φLH
t4
t2
t6
t1
t7
t14
t5
t7
t3
t6
t15
t17
φ2
φRS
OUT-ODD
V
VOUT-EVEN
t9
t12
t16
t13
t10
t11
t8
Clock timing of φ1, φ2, φLH, φRS, and VOUT at odd or even are the same as timing chart 3 in the case of
alternate output.
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Clock Timing Chart 4
Cross point φ1 and φ2
5V
φ1
0V
φ2
Cross point φLH and φ2
φ2
5V
ILX510
1.5V (Min.) 1.5V (Min.)
φLH
2.0V (Min.) 0.5V (Min.)
0V
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ILX510
2622
D93
D83
D81
D79
D77
D75
S5149
S5147
S5145
S3
S1
D73
D71
D69
D27
D25
D23
D94
D84
D82
D80
D78
D76
S5150
S5148
S5146
S4
S2
D74
D72
D70
D28
D26
D24
1-line output period (5244 pixels)
Optical black (48 pixels)
3
2
1
5
0
5
0
5
0
5
0
5
φ1-ODD
φROG
φLH-ODD
φ2-ODD
φ1-EVEN
φLH-EVEN
Clock Timing Chart 5 (alternate output)
0
EVEN
φ2-
5
0
φRS-ODD
—8—
D5
D3
D1
VOUT-ODD
5
φRS-EVEN
D6
D4
D2
Dummy signal (74 pixels)
0
VOUT-EVEN
Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles.
∗Alternate output is available by making φ1-EVEN, φ2-EVEN, φLH-EVEN, φRS-EVEN delayed to φ1-ODD, φ2-ODD, φLH-ODD, φRS-ODD for half a cycle.
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Clock Pulse Recommended Timing
Symbol Min. Typ. Max. Unit
φROG, φ1pulse timing t1 50 100 — ns
φROG pulse high level period t2 600 1000 — ns
φROG, φ1 pulse timing t3 400 1000 — ns
φROG pulse rise time t4 0 5 10 ns
φROG pulse fall time t5 0 5 10 ns
φ1 pulse rise time /φ2 pulse fall time t6 0 20 60 ns
φ1 pulse fall time / φ2 pulse rise time t7 0 20 60 ns
φRS pulse high level period t8 20 250
φRS, φLH pulse timing t9 0 250
∗
∗
—ns
—ns
φRS pulse rise time t10 0 10 30 ns
φRS pulse fall time t11 0 10 30 ns
Signal output delay time
t12 — 8 — ns
t13 — 8 — ns
φ1, φLH pulse low level period/φ2 pulse high level period t14, t16 25 500
φ1, φLH pulse high level period/φ2 pulse low level period t15, t17 25 500
∗
∗
—ns
—ns
ILX510
(∗) These timing is the recommended condition under fφ1=1 MHz.
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IC1 :74AC04
Tr1 : 2SC2785
ILX510
ROG
φ
5.1kΩ
IC1
OUT-EVEN
V
Tr1
V
φ ROG
DD
IC1
-EVEN
-EVEN
φ 1
φ 1
φ 2
-ODD
2
-ODD
10 11
φ
2Ω
φ1
φ 2
2Ω
-ODD
-ODD
GND
NC
φ LH
φ RS
100Ω
φ LH
φ RS
NC
NC
-EVEN
-EVEN
LH
φ
φ RS
100Ω
V
V
DD
DD
Tr1
V
V
OUT-EVEN
OUT-ODD
5.1kΩ
100Ω
V
GND
GG
100Ω
VOUT-ODD
Application Circuit ∗ (inphase output)
GND
22 21 20 19 18 17 16 15 14 13 12
NC
1 2 3 4 5 6 7 8 9
47µF/16V
R = 2 MHz
0.1µF
12V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
0.1µF
∗Data rate fφ
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Example of Representative Characteristics (VDD = 12 V, Ta = 25 °C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
0.8
0.6
0.4
Relative sensitivity
0.2
0
400 500 600 700 800 900 1000
WAVELENGTH (nm)
MTF of main scanning direction (Standard characteristics)
Spatial frequency (cycles/mm)
0 14.3 28.6 42.9 57.1 71.4
1.0
ILX510
0.8
0.6
MTF
0.4
0.2
0
0
Dark signal output temperature characteristics
10
5
1
0.5
Output voltage rate
(Standard characteristics)
0.2 0.4 0.6 0.8 1.0
Normalized spatial frequency
Integration time output voltage characteristics
(Standard characteristics)
1
0.5
Output voltage rate
0.1
01020304050
Ta-Ambient temperture (°C)
60
0.1
1510
τ int-integration time (ms)
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ILX510
Operational frequency response of supply supply current
30
20
-supply current (mA)
DD
IV
10
0
10
(Standard characteristics)
20 40
Data rate fø
Offset level vs. V
DD characteristics
(Standard characteristics)
Ta = 25°C
R (MHz)
Ta = 25°C
8
6
-Offset level (V)
4
OS
V
2
0
10
8
6
-Offset level (V)
OS
4
V
∆V
OS
~
∆VDD
–0.2
12.0 12.611.4
DD (V)
V
Offset level vs. Temperature characteristics
(Standard characteristics)
∆VOS
∆Ta
8 mV/°C
~
2
20 40 600
30 5010
Ta-Ambient temperature (°C)
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Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-DIP Packages
The following points should be observed when handling and installing cer-DIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1)Compressive strength:39 N/surface (Do not apply load more than 0.7 mm inside the outer perimeter
of the glass portion.)
(2)Shearing strength: 29 N/surface
(3)Tensile strength: 29 N/surface
(4)Torsional strength: 0.9 Nm
ILX510
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
Upper ceramic layer
Lower ceramic layer
39N
Low-melting glass
(1)
29N
(2)
29N
(3)
0.9Nm
(4)
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1)Applying repetitive bending stress to the external leads.
(2)Applying heat to the external leads for an extended period of time with soldering iron
(3)Rapid cooling or heating
(4)Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80 °C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30
W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
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ILX510
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to
scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Package Outline Unit : mm
11.12 ± 0.5
22
22pin DIP (400mil)
55.7 ± 0.5
36.05 (7µm × 5150Pixels)
ILX510
12
0° to 9°
V
5.0 ± 0.5
4.0 ± 0.5
H
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
No.1 Pixel
1
Cer-DIP
TIN PLATING
42 ALLOY
7.1g
2.54
54.2
9.0
10.0 ± 0.5
11
0.3
3.58
4.38 ± 0.5
M
0.51
10.16
(AT STAND OFF)
1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.
2. The thickness of the cover glass is 0.8mm, and the refractive
index is 1.5.
0.25
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