Datasheet ILX508A Datasheet (Sony)

7926-pixel CCD Linear Image Sensor (B/W)

For the availability of this product, please contact the sales office.

Description

The ILX508A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition reset pulse can switch between internal generation and external input.

Features

• Number of effective pixels: 7926 pixels

• Pixel size: 7µm × 7µm (7µm pitch)

• Built-in timing generator and clock-drivers

• Ultra high sensitivity

• Ultra low lag/low dark voltage

• Output method

• Maximum operating frequency: 12.5MHz

ILX508A

24 pin DIP (Ceramic)

Absolute Maximum Ratings

• Supply voltage VDD1 11 V

VDD2 6V

•Operation temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

1

GG

Pin Configuration (Top View)

V

GND

VDD1

VOUT

GND

φROG

DD2

V

VDD2

RSSW

T1

2

3

4

5

6

7

8

9

10

1

24

23

22

21

20

19

18

17

16

15

φCLK

V

DD1

RS/SH

DD1

V

DD1

GND

DD2

V

GND

T4

T3

11

GND

12

NC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

7926

14

13

T2

NC

– 1 –

E96X33-PS

ILX508A

NC 12

13

NCT2T3T4GNDV

D116

1415

16

D115

pulse generator

D99

S7926 S7925

Mode selector Read out gate

6

11

10

22

9

DD2GNDVDD1VDD1VDD1

17

18

19

20

21

23

Clock-drivers

CCD analog shift register

Read out gate

S2 S1

D98

D18

D17

Read out gate

CCD analog shift register

Clock-drivers

24

8

Clock-pulse generator

Sample-and-hold pulse generator

7

5

3

VDD1GND VDD2GND φCLKVDD2 RSSW RS/SH T1 GND φROG

Block Diagram

• Output amplifier

• Sample-and-hold circuit

• Feed through suppression

circuit

4

OUT

V

– 2 –

2

1

VGG

Pin Description

ILX508A

Pin No.

1 2 3 4 5 6 7 8

9

10 11 12 13 14 15

Symbol VGG GND VDD1 VOUT GND φROG VDD2 VDD2

RSSW T1

GND NC NC T2 T3

Description Output circuit gate bias GND 9V power supply Signal output GND Clock pulse 5V power supply 5V power supply RS pulse external, internal selection

∗

(External RS → VDD1, Internal RS → GND) Test pin (5V) GND NC NC Test pin (GND) Test pin (5V)

16 17 18 19 20 21 22 23 24

∗

Output mode is changeable as follows.

9pin GND

VDD1

22pin

T4 GND VDD2 GND VDD1 VDD1 RS/SH VDD1 φCLK

Internal RS without S/H

Test pin (GND) GND 5V power supply GND 9V power supply 9V power supply

∗

Clock pulse or S/H switch 9V power supply Clock pulse

GND

Internal RS

with S/H

—

VDD1

—

φRS

—

External RS

without S/H

– 3 –

Recommended Voltage

ILX508A

Item VDD1 VDD2

Min.

8.5

4.75

Typ.

9.0

5.0

Max.

9.5

5.25

Note) Rules for raising and lowering power supply voltage.

To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

Clock Characteristics

Item Input capacity of φCLK Input capacity of φROG Input capacity of RS/SH

φCLK frequency φRS frequency

Symbol CφCLK CφROG C RS/SH fφCLK fφRS

Min.

— — — — —

Typ.

10 10 10

1 1

Unit

V V

Max.

— — —

12.5

Unit

pF pF

pF MHz MHz

– 4 –

ILX508A

Electrooptical Characteristics

∗1

(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Light source = 3200K, φCLK = 1MHz, Internal φRS mode without S/H,

IR cut filter, CM-500S (t = 1.0mm))

Item Sensitivity1 Sensitivity2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level

DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency

Symbol R1 R2 PRNU VSAT SE

∆V VDRK

DSNU IL IVDD1 IVDD2 TTE

Min.

7.5 — —

1.0

0.072 — —

— — — — 90

Typ.

10.8

24.6 5

1.5

0.139

1.0

0.3

0.6

0.02

16

5

97

Max.

13.9 —

12.5 — —

10.0

2

5 — 32 16 —

Unit V/(lx · s) V/(lx · s)

%

V

lx · s

mV mV

mV

% mA mA

%

Remarks

∗2 ∗3 ∗4 ∗5 ∗6

∗7 ∗8

∗9

∗10

— —

— Output impedance Offset level Dynamic range

∗1

In accorcance with the given electrooptical characteristics, the even black level is defined as the mean

ZO VOS DR

— —

500

600

3.0

5000

— — —

Ω

V

—

value of D8, D10, D12, D14, and D16.

∗2

For the sensitivity test light is applied with a uniform intensity of illumination.

∗3

W lamp (2854K).

∗4

PRNU is defined as indicated below. Ray incidence conditions are the same as for ∗2.

PRNU = × 100 [%]

(VMAX – VMIN)/2

VAVE

Where the 7926 pixels are divided into blocks of 102, even and odd pixels, respectively (Even and odd last blocks are 87.) The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.

∗5

Use below the minimum value of the saturation output voltage.

∗6

Saturation exposure is defined as follows.

VSAT

SE =

R1

—

∗11 ∗12

∗7

Indicates the DC difference in value between odd black level and even black level.

∗8

optical signal accumulated time τ int stands at 10ms.

∗9

The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms.

∗10

VOUT = 500mV (Typ.)

– 5 –

∗11

VOS is defined as indicated below.

Vout

V

OS

GND

∗12

Dynamic range is defined as follows.

VSAT

DR =

VDRK

When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage.

ILX508A

– 6 –

10µ/10V0.01µ

ILX508A

φRS

13

14

15

16

17

18

19

20

21

22

23

NC

(D)

(A)

(D)

T2 (D)

T3 (D)

T4 (D)

GND (D)

DD2

V

GND (D)

DD1

V

DD1

V

RS/SH (D)

DD1

V

(D)

(A)

NC

12

GND (A)

11

T1 (D)

10

PSSW (D)

9

DD2

V

8

DD2

V

7

φROG

6

GND (A)

5

OUT

V

4

DD1

V

3

GND (A)

2

φROG

When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and

pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance.

∗

2SA1175

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

1kΩ

Application Circuit (External φRS)

φCLK

9V

5V

24

φCLK

GG

(A)

– 7 –

V

1

10µ/16V

Output signal

0.01µ

10µ/16V

0.01µ

ILX508A

2

1

8042

D116 D109 D108

D107 D106 D100

D99 D7926 D7925

D7924 D7923

S4 S3 S2 S1 D98 D97 D96

D20

D19 D18 D17

D16

Dummy signal

Effective picture

(80 pixels)

Optical black

(18 pixels)

(7926 pixels)

elements signal

1 line output period (8042 pixels)

Clock Timing Diagram (External φRS)

D6

D5

4

3 2

1

5

0

φROG

5

0

φCLK

0

φRS

D4 D3

D2

D1

VOUT

Dummy signal (98 pixels)

– 8 –

Clock pulse Waveform Conditions

φCLK, φROG pulse related

ILX508A

t8 t9

Internal φRS mode

φCLK

φROG

φCLK

t8 t9

t2

t1

t3

t5t4

External φRS mode

φCLK

Vout

φRS

t10t10

t11

t5t4

t9 t8

t6t7

t13

t10

t12

– 9 –

ILX508A

Item

φROG, φCLK pulse timing φROG, φCLK pulse timing φROG pulse high level period φCLK pulse high level period φCLK pulse low level period φRS pulse low level period φCLK, φRS pulse timing

Input clock pulse rise/fall time

Input clock pulse voltage

Signal output delay time

∗

1

The frequency of φCLK is 1MHz.

High level Low level

Internal φRS

External φRS

Symbol t1 t3 t2 t4 t5 t6 t7 t8, t9 VφCLK, VφROG VφRS t10 t11 t12 t13

Min.

200 1200 1200

40 40 25 60 —

4.5 0

— — — —

Typ.

300 1500 1500

500 500 100 550

5

5.0 — 95 70 45 60

∗

1

∗

1

∗

1

∗

1

10 + t4 + t5

Max.

— — — — — —

10

5.5

0.5 — — — —

Unit

ns ns ns ns ns ns ns ns

V

V ns ns ns ns

– 10 –

Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C)

Spectral sensitivity characteristics (Standard characteristics)

1.0

0.8

0.6

0.4

Relative sensitivity

0.2

0

400 500 600 700 800 900 1000

Wavelength [nm]

MTF of main scanning direction (Standard characteristics)

Spatial frequency [cycle/mm]

0 14.3 28.6 42.9 57.1 71.4

1.0

ILX508A

0.8

0.6

MTF

0.4

0.2

0

0.2 0.4 0.6 0.8 1.0 Normalized spatial frequency

Dark signal output temperature characteristics

(Typical characteristics)

10

5

1

Integration time output voltage characteristics

(Typical characteristics)

1

0.5

Output voltage rate

0.5

0.1 0

10 20 30 40 60

Ta – Ambient temperature [°C]

Output voltage rate

0.1

50 1

– 11 –

5

τ int – integration time [ms]

10

ILX508A

Operational frequency characteristics of the VDD1 supply current (Typical characteristics)

15

10

supply current [mA]

DD1

– V

5

DD1

IV

0

2 4 6 8 12.5

fφCLK – φCLK clock frequency [MHz]

Offset level vs. V

DD1 characteristics

10

(Typical characteristics)

6

Ta = 25°C

5

Operational frequency characteristics of the VDD2 supply current (Typical characteristics)

60

50

40

30

supply current [mA]

DD2

20

– V

DD2

IV

10

0

2 4 6 8 12.5

fφCLK – φCLK clock frequency [MHz]

10

Offset level vs. VDD2 characteristics

(Typical characteristics)

6

Ta = 25°C

5

4

3

– Offset level [V]

2

OS

V

1

0

∆V

OS

~

0.35

∆VDD1

8.5 9 9.5 VDD1 [V]

–

Offset level vs. Temperature characteristics

(Typical characteristics)

6

5

4

3

– Offset level [V]

2

OS

V

1

– Offset level [V]

OS

V

∆VOS

∆Ta

~

– 0.8mV/°C

–

4

3

2

1

0

4.75 5 5.25

∆VOS

∆VDD2

VDD2 [V]

~

–

–0.14

0

10 20 30 40 60

Ta – Ambient temperature [°C]

50

– 12 –

Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates use boxes treated for the prevention of static charges.

2) Regulation for raising and lowering the power supply voltage. When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V).

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W

soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficienty.

c) To dismount an imaging device do not use a solder suction equipment.

When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.

ILX508A

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained.

Be careful not to scratch the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 13 –

0 ° to 9 °

ILX508A

0.25 -0.05

+0.1

10.16 ± 0.3 (AT STAND OFF)

13

71.0 ± 0.9

24Pin DIP (400mil)

55.482 (7µm × 7926Pixels) 24

10.0 ± 0.5

9.0 ± 0.15

12

68.0 ± 0.15

1

No.1 Pixel

0.8 ± 0.1

1.27

2.29

3.1 ± 0.5

0.46 ± 0.15

2.54 ± 0.25

0.97 ± 0.3

M

1. The height from the bottom to the sensor surface is 1.42 ± 0.3mm.

2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.

0.3

Package Outline Unit: mm

9.21 ± 0.8

GOLD PLATING

Ceramic

5.8g

42ALLOY

H

V

5.0 ± 0.5

1st. pin Index

4.0 ± 0.5

PACKAGE MATERIAL

LEAD TREATMENT

PACKAGE WEIGHT

LEAD MATERIAL

PACKAGE STRUCTURE

– 14 –