Datasheet ILX506 Datasheet (Sony)

Page 1

5000-pixel CCD Linear Image Sensor (B/W)

For the availability of this product, please contact the sales office.

Description

The ILX506 is a reduction type CCD linear sensor developed for high resolution facsimiles and copiers. This sensor reads A3-size documents at a density of 400 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition, reset pulse can be switched between internal generation and external input.

Features

• Number of effective pixels: 5000 pixels

• Pixel size: 7µm × 7µm (7µm pitch)

• Built-in timing generator and clock-drivers

• Ultra low lag/ultra high sensitivity/low dark output

• Single output method

• Maximum clock frequency: 12.5MHz

ILX506

22 pin DIP (Ceramic)

Absolute Maximum Ratings

• Supply voltage VDD1 11 V

VDD2 6V

•Operating temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

Pin Configuration (Top View)

V GND V

DD1

VOUT GND

φROG

DD2

VDD2

RSSW

GND

10 11

1 2 3 4 5 6 7 8 9

5000

22 21 20 19 18 17 16 15 14 13 12

φCLK VDD1 RS/SH V

DD1

VDD1 GND V

DD2

GND T4 T3 T2

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E92239B78-PS

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ILX506

DD2

DD1

GND

1415

Clock-drivers

Read out gate

CCD analog shift register

D34 D33 D32

D31 D30 D29

S5000 S4999

Read out gate

D28

D18 D17

Read out gate

pulse generator

Mode

selector

Clock-drivers

CCD analog shift register

Clock pulse generator

Sample-and-hold pulse generator

DD2

φROG

GND

RS/SH

RSSW

φCLK

GND

Block Diagram

• Output amplifier

• Sample-and-hold circuit

• Feed through

suppression circuit

VOUT

VGG

– 2 –

DD1

GND

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Pin Description

ILX506

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

Symbol VGG GND VDD1 VOUT GND φROG VDD2 VDD2 RSSW T1 GND T2 T3 T4 GND VDD2

Output circuit gate bias GND 9V power supply Signal output GND Clock pulse 5V power supply 5V power supply

∗1

Reset pulse switchover pin Test pin (5V) GND Test pin (GND) Test pin (5V) Test pin (GND) GND 5V power supply

Description

17 18 19 20 21 22

∗1

Output mode is changeable as follows.

9pin

GND

VDD1

20pin

GND VDD1 VDD1 RS/SH VDD1 φCLK

Internal RS without S/H

GND 9V power supply 9V power supply

∗1

Clock pulse or with S/H; without S/H switch 9V power supply Clock pulse

GND

—

VDD1

Internal RS

with S/H

—

φRS

—

External RS

without S/H

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Recommended Voltage

ILX506

Item VDD1 VDD2

Min.

8.5

4.75

Typ.

9.0

5.0

Max.

9.5

5.25

Unit

V V

Note) Rules for raising and lowering power supply voltage

To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

Clock Characteristics

Item Input capacity of φCLK pin Input capacity of φROG pin Input capacity of RS/SH pin Frequency of φCLK Frequency of φRS

Symbol CφCLK CφROG CRS/SH fφCLK fφRS

Min.

— — — — —

Typ.

10 10 10

1 1

Max.

— — —

12.5

Unit

pF pF

pF MHz MHz

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Electro-optical Characteristics (Note 1)

(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, φCLK = 1MHz, Internal φRS mode without S/H,

ILX506

Light source = 3200K, IR cut filter, CM-500S (t = 1.0mm))

Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Dynamic range

Symbol R1 R2 PRNU VSAT SE ∆V VDRK DSNU IL IVDD1 IVDD2 TTE ZO VOS DR

Min.

7.5 — —

1.0

0.072 — — — — — — 92 — —

500

Typ.

10.8

24.6 4

1.5

0.139

1.0

0.3

0.6

0.02

600

3.0

5000

Max.

13.9 — 10 — —

10.0

3 — 32

7 — — — —

Unit V/(lx · s) V/(lx · s)

lx · s

mV mV mV

% mA mA

Ω

—

Remarks

Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9

Note 10

— — —

— Note 11 Note 12

Notes)

1) In accordance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12 to D14. The odd black level is defined as the mean value of D7 , D9, D11 and D13.

2) For the sensitivity test light is applied with a uniform intensity of illumination.

3) W lamp (2854K)

4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.

PRNU = × 100 [%]

(VMAX – VMIN)/2

VAVE

Where the 5000 pixels are divided into blocks of 100, even and odd pixels, respectively. The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.

5) Use below the minimum value of the saturation output voltage.

6) Saturation exposure is defined as follows.

SE =

VSAT

7) Indicates the DC difference in value between odd black level and even black level.

8) Optical signal accumulated time τ int stands at 10ms.

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ILX506

9) The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms.

10) VOUT = 500mV (Typ.)

11) Vos is defined as indicated below.

Vout

GND

12) Dynamic range is defined as follows.

DR =

VSAT VDRK

When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time.

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1222 21 20 19 18 17 16 15 14 13

(D)

(A)

ILX506

10µ/10V

0.01µ

GND

φRSφCLK

(D)

GND

(D)

VDD2

(D)

GND

(A)

VDD1

(A)

VDD1

(D)

RS/SH

DD1

(D)

(A)

RSSW

VDD2

DD2

φROG

GND

VOUT

VDD1

GND

φROG

When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and

This application circuit shows when φRS is used externally.

2SA1175

1kΩ

∗

pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance.

( )

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

∗

Application Circuit

φCLK

– 7 –

(A)

VGG

1 2 3 4 5 6 7 8 9 10 11

10µ/16V

Output signal

0.01µ

10µ/16V

0.01µ

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ILX506

5034

D34 D33 D32

D31 D30 D29

S5000 S4999 S4998 S4997

S4 S3 S2 S1 D28 D27 D26

D18 D17 D16

D15 D14

Dummy signal

(6 pixels)

Effective picture

elements signal

(5000 pixels)

Optical black

(28 pixels)

This clock timing diagram shows when φRS is used externally.

∗

1-line output period (5034 pixels)

∗

Clock Timing Diagram

φROG

4 3 2

φCLK

φRS

D4 D3

VOUT

Dummy signal (28 pixels)

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Clock Pulse Waveform Conditions

φCLK, φROG pulse related

ILX506

Internal φRS mode

φCLK

φROG

φCLK

t8 t9

t1 t3

t4 t5

External φRS mode

Vout

φCLK

φRS

t11

t4 t5

t8t9

t7 t6

t13

t10t10

t10

t12

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ILX506

Item

φROG, φCLK pulse timing φROG, φCLK pulse timing φROG pulse high level period φCLK pulse high level period φCLK pulse low level period φRS pulse low level period φCLK, φRS pulse timing

Input clock pulse rise/fall time

High level

Input clock pulse voltage

Low level

Internal φRS

Signal output delay time

External φRS

∗1

Recommended condition during φCLK = 1MHz.

Symbol t1 t3 t2 t4 t5 t6 t7 t8, t9 VφCLK, VφROG VφRS t10 t11 t12 t13

Min.

100 800 800

40 40 25 60 —

4.5 0

— — — —

Typ.

200 1000 1000

500 500 100 550

5.0 — 95 70 45 60

∗1 ∗1 ∗1 ∗1

10 + t4 + t5

Max.

— — — — — —

5.5

0.5 — — — —

Unit

ns ns ns ns ns ns ns ns

V ns ns ns ns

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Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C)

Spectral sensitivity characteristics

(Standard characteristics)

1.0

0.8

0.6

0.4

Relative sensitivity

0.2

400 500 600 700 800 900 1000

Wavelength [nm]

MTF of main scanning direction (Standard characteristics)

Spatial frequency [cycles/mm]

1.0

14.3 28.6 42.9 57.1 71.4

ILX506

0.8

0.6

MTF

0.4

0.2

Dark signal output temperature characteristics

(Standard characteristics)

Output voltage rate

0.5

0.2 0.4 0.6 0.8 1.0 Normalized spatial frequency

Integration time output voltage characteristics

(Standard characteristics)

0.5

Output voltage rate

0.1 0

10 20 30 40 6050

Ta – Ambient temperature [°C]

– 11 –

0.1 1

τ int – Integration time [ms]

105

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ILX506

Operational frequency characteristics of the VDD1

supply current (Standard characteristics)

supply current [mA]

DD1

– V

DD1

2 4 6 8 12.510

fφCLK – φCLK clock frequency [MHz]

Offset level vs. VDD1 characteristics

(Standard characteristics)

Ta = 25°C

Operational frequency characteristics of the VDD2

supply current (Standard characteristics)

supply current [mA]

DD2

– V

DD2

2468 12.510

fφCLK – φCLK clock frequency [MHz]

Offset level vs. VDD2 characteristics

(Standard characteristics)

Ta = 25°C

Vos – Offset level [V]

∆Vos

∆VDD1

8.5 9 9.5 VDD1 [V]

0.35

Offset level vs. Temperature characteristics

(Standard characteristics)

Vos – Offset level [V]

∆Vos

∆Ta

–0.8mV/°C

∆Vos

∆V

4.75 5 5.25 VDD2 [V]

DD2

–0.14

0305010

20 40 60

Ta – Ambient temperature [°C]

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Notes on Handling

1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V).

3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficienty.

c) To dismount an image sensor, do not use a solder suction equipment.

When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type.

ILX506

4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the grease stained.

Be careful not to scratch the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

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0° to 9°

ILX506

(AT STAND OFF)

10.16

0.25

22pin DIP (400mil)

49.0 ± 0.5

35.0 (7µm × 5000Pixels)

8.2 ± 0.8

10.0 ± 0.5

8.1

No.1 pixel

1. The height from the bottom to the sensor surface is 1.42 ± 0.3mm.

2. The thickness of the cover glass is 0.8mm, and the refractive

 index is 1.5.

3.1 ± 0.5

2.3

0.51

0.3

2.54

111

1st. pin index

Ceramic

TIN PLATING

42 ALLOY

3.9g

Package Outline Unit: mm

5.0 ± 0.5

0.97

4.0 ± 0.5

PACKAGE MATERIAL

LEAD TREATMENT

PACKAGE WEIGHT

LEAD MATERIAL

PACKAGE STRUCTURE

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