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2592-pixel CCD Linear Image Sensor (B/W)
For the availability of this product, please contact the sales office.
Description
The ILX505A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads A3 size documents at a density of
200 DPI (Dot Per Inch). A built-in timing generator
and clock-drivers ensure direct drive at 5V logic for
easy use.
Features
• Number of effective pixels: 2592 pixels
• Pixel size: 11µm × 11µm (11µm pitch)
• Built-in timing generator and clock-drivers
• Ultra low lag
• High sensitivity
• Maximum clock frequency: 5MHz
ILX505A
22 pin DIP (Ceramic)
Absolute Maximum Ratings
• Supply voltage VDD1 11 V
VDD2 6V
•Operating temperature –10 to +55 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
OUT
V
GND
GND
SHSW
φCLK
DD1
V
GND
DD2
V
T1
EXRS
φROG
10
11
1
2
3
4
5
6
7
8
9
1
2592
22
21
20
19
18
17
16
15
14
13
12
DD2
V
NC
VDD1
RSSW
VGG
GND
GND
VDD1
NC
NC
GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E92Y22D78-PS
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ILX505A
DD1
DD1
GND
NC
NC
V
GND
GND
V
12
13
1415
16
17
20
D39
D38
D37
D36
D35
D34
S2592
S2591
S2
S1
D33
D15
D14
Read out gate
CCD analog shift register
Clock-drivers
Read out gate
pulse generator
Mode
selector
11
4
10
19
5
9
φROG
SHSW
EXRS
RSSW
φCLK
T1
Block Diagram
DD2
NC
V
21
22
Output amplifier
Sample-and-hold
circuit
1
VOUT
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18
VGG
8
Clock pulse generator
Sample-and-hold pulse
generator
7
6
3
2
DD2
DD1
V
GND
V
GND
GND
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Pin Description
ILX505A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Symbol
VOUT
GND
GND
SHSW
φCLK
VDD1
GND
VDD2
T1
EXRS
φROG
GND
NC
NC
Description
Signal output
GND
GND
Switch
Clock pulse
9V power supply
GND
5V power supply
Test pin (VDD2)
External RS pulse input. Must be connected to
VDD2 when the internal RS pulse is used.
Clock pulse
GND
NC
NC
with S/H → GND
{
without S/H → VDD2
15
16
17
18
19
20
21
22
VDD1
GND
GND
VGG
RSSW
VDD1
NC
VDD2
9V power supply
GND
GND
Output circuit gate bias
Reset pulse switchover pin
9V power supply
NC
5V power supply
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Mode Description
ILX505A
Mode in Use
Internal RS
Externel RS
19 pin RSSW
GND
VDD2
10 pin EXRS
VDD2
φRS
Note) When the external RS mode is in use, operation of use internal S/H is not guaranteed. Pin 4 must be
connected to 5V DC power supply.
Recommended Voltage
Item
VDD1
VDD2
Min.
8.5
4.75
Typ.
9.0
5.0
Max.
9.5
5.25
Unit
V
V
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
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Electro-optical Characteristics
ILX505A
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz,
Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)),
When Internal RS (Pin 19 = GND, Pin 10 = VDD2)
Item
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
9V supply current
5V supply current
Total transfer efficiency
Output impedance
Offset level
Symbol
R1
R2
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD1
IVDD2
TTE
ZO
VOS
Min.
16.8
—
—
1.5
—
—
—
—
—
—
—
92.0
—
—
Typ.
21
53
2.0
1.8
0.3
0.5
0.02
6000
0.085
14.0
5.0
97.0
600
4.5
Max.
25.2
—
8.0
—
2.0
3.0
—
—
—
20.0
10.0
—
—
—
V/(lx · s)
V/(lx · s)
Notes)
1) For the sensitivity test light is applied with a uniform intensity of illumination.
2) W lamp (2854K)
3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
Unit
%
V
mV
mV
%
—
lx · s
mA
mA
%
Ω
V
Remarks
Note 1
Note 2
Note 3
—
Note 4
Note 4
Note 5
Note 6
Note 7
—
—
—
—
Note 8
PRNU = × 100 [%]
(VMAX – VMIN)/2
VAVE
The maximum output of all the valid pixels is set to VMAX, the minimum output to VMIN and the average
output to VAVE.
4) Integration time is 10ms.
5) VOUT = 500mV
6) DR = VSAT/VDRK
7) SE = VSAT/R1
8) VOS is defined as indicated below.
Signal is observed at PNP-type emitter follower out.
D32 D33 S1D31
OS
OS
V
GND
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ILX505A
2
1
2631
D39
D38
D37
D36
D35
D34
S2592
S2591
S2590
S2589
S4
S3
S2
S1
D33
D32
D31
D15
D14
D13
D12
D11
Dummy signal
(6 pixels)
Effective picture
elements signal
(2592 pixels)
Optical black
(18 pixels)
Internal S/H is not in use
∗
1-line output period (2631 pixels)
5
φROG
Clock Timing Diagram (For internal RS mode)
D6
D5
4
3
2
1
0
5
0
φCLK
D4
D3
D2
D1
∗
OUT
V
Dummy signal (33 pixels)
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ILX505A
2
1
2631
D39
D38
D37
D36
D35
D34
S2592
S2591
S2590
S2589
S4
S3
S2
S1
D33
D32
D31
D15
D14
D13
D12
D11
Dummy signal
(6 pixels)
Effective picture
elements signal
(2592 pixels)
Optical black
(18 pixels)
1-line output period (2631 pixels)
5
φROG
Clock Timing Diagram (For external RS mode)
D6
D5
4
3
2
1
0
5
φCLK
0
5
0
φRS
D4
D3
D2
OUT
V
Dummy signal (33 pixels)
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φCLK, VOUT Timing (For internal RS mode)
t1 t2
φCLK
t3 t4
VOUT
t17
ILX505A
t10
Item
φCLK pulse rise/fall time
φCLK pulse duty
∗1
φCLK – VOUT 1
φCLK – VOUT 2
∗1
100 × t3/(t3 + t4)
Symbol
t1, t2
t10
t17
—
Min.
0
40
50
30
Typ.
10
50
80
75
Max.
—
60
110
120
Unit
ns
%
ns
ns
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φCLK, φRS, VOUT Timing (For external RS mode)
t1 t2
φCLK
t3 t4
t5
φRS
t8 t9
t7t6
t11
VOUT
ILX505A
t10
Item
φCLK, φRS pulse rise/fall time
φCLK pulse duty
∗1
φCLK – φRS pulse timing
φCLK – φRS pulse timing
φRS pulse period
φCLK – VOUT
φRS – VOUT
∗1
100 × t3/(t3 + t4)
Symbol
t1, t2, t8, t9
—
t6
t7
t5
t10
t11
Min.
0
40
0
50
50
50
30
Typ.
10
50
100
100
100
80
50
Max.
—
60
—
—
—
110
70
Unit
ns
%
ns
ns
ns
ns
ns
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φROG, φCLK Timing
φROG
φCLK
t12
ILX505A
t15t13 t14
t16
Item
φROG, φCLK pulse timing
φROG pulse rise/fall time
φROG pulse period
Symbol
t12, t16
t13, t15
t14
Min.
500
0
500
Typ.
1000
10
1000
Max.
—
—
—
Unit
ns
ns
ns
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Example of Representative Characteristics
Spectral sensitivity characteristics
(Standard characteristics)
ILX505A
1.0
10
9
8
7
6
5
4
Relative sensitivity
3
2
1
0
400 500 600 700 800 900 1000
MTF of main scanning direction
(Standard characteristics)
Spatial frequency [cycles/mm]
0
9.1 18.2 27.3 36.4 45.5
λ = 560nm
Wavelength [nm]
1.0
Ta = 25°C
MTF of sub scanning direction
(Standard characteristics)
Spatial frequency [cycles/mm]
0
9.1 18.2 27.3 36.4 45.5
λ = 560nm
0.8
0.6
X-MTF
0.4
0.2
0
0.8
0.6
Y-MTF
0.4
0.2
0
0.2 0.4 0.6 0.8 1.0
Normalized spatial frequency
0
0
0.2 0.4 0.6 0.8 1.0
Normalized spatial frequency
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Application Circuit
ILX505A
5V
9V
1000p
V
OUT
10µ
1000p 10µ
(A) (A) (D)(A) (D) (D) (D)
1 2 3 4 5 6 7 8 9 10 11
9V
3k
2SA1175
(D) (A)
100
10µ
10µ1000p
1222 21 20 19 18 17 16 15 14 13
(D) (D) (D)(A)(A)(A)(A)(A)(A)(D)
10µ
φCLK φROG
1000p
1000p
10µ
5V
• Internal S/H is in use. Pin 4 must be connected to 5V DC power supply when S/H is not used.
• Internal RS mode is used. For the external RS mode, connect Pin 19 and Pin 4 to 5V DC power supply and
input a proper clock pulse into Pin 10.
• When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply
and pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large
capacitance.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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Page 13
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Regulation for raising and lowering the power supply voltage
When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and
then VDD1 (9V).
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
ILX505A
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air
is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
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Page 14
0° to 9°
0.25
10.16
(AT STAND OFF)
10.0 ± 0.5
9.0
1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm.
2. The thickness of the cover glass is 0.7mm, and the refractive
index is 1.5.
2.6
M
3.3 ± 0.5
0.3
ILX505A
12
22pin DIP (400mil)
41.6 ± 0.5
28.512 (11µm X 2592Pixels)
22
7.6 ± 0.8
40.2
No.1 Pixel
111
H
V
5.0 ± 0.5
4.0 ± 0.5
0.512.54
Cer-DIP
PACKAGE MATERIAL
PACKAGE STRUCTURE
42 ALLOY
TIN PLATING
LEAD TREATMENT
3.9g
PACKAGE WEIGHT
LEAD MATERIAL
Package Outline Unit: mm
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