Datasheet ILX128MA Datasheet (Sony)

5350-pixel × 6-line CCD Linear Sensor (Color)

Description

The ILX128MA is a reduction type CCD linear
sensor developed for color image scanner, and has
shutter function per each color. This sensor reads
A3-size documents at a density of pseudo 800DPI,
and reads A4-size at a density of pseudo 1200DPI.

Features

• Number of effective pixels:

32100 pixels (5350 pixels × 6)

• Pixel size: 6µm × 8µm (8µm pitch)

• Distance between line:

48µm (6 lines: Rsub – Rmain,
Rmain – Gsub, Gsub – Gmain,
Gmain – Bsub, Bsub – Bmain)

• Single-sided readout

• Shutter function

• Ultra-high sensitivity/Ultra-low lag

• Supply voltage: Single 12V power supply

• Input clock pulse: CMOS 5V drive

• Number of output: 3 (R, G, B)

• Package: 24-pin Plastic-DIP

Absolute Maximum Ratings

• Supply voltage VDD 15 V

• Input clock voltage 7 V

• Operating temperature –10 to +55 °C

• Storage temperature –30 to +80 °C

– 1 –

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

ILX128MA

24 pin DIP (Plastic)

1
2
3
4
5
6

7
8

9
10
11
12

13

14

15

16

17

18

19

20

21

22

23

24

φ1L

φ1L'

φRS

V

OUT-R

5350 R (Sub) 1

5350 R (Main) 1

5350 G (Sub) 1

5350 G (Main) 1

5350 B (Sub) 1

5350 B (Main) 1

VOUT-G

VDD

NC
NC

GND

φ2

φSHUT

-B

φSHUT-G

φ4
φ2L
φ3

GND
V

OUT-B

NC

NC
V

DD

NC

φ1
φROG
φSHUT

-R

Pin Configuration (Top View)

E00462-PS

For the availability of this product, please contact the sales office.

– 2 –

ILX128MA

S5350

D41

D44

S3

Main Line (Blue)

CCD register

CCD register

CCD register

CCD register

CCD register

CCD register

S2
S1

D40

D24

S5350

D41

D44

S3

Main Line (Green)

S2
S1

D40

D24

S5350'

D41'

D44'

S3'

Sub Line (Blue)

S2'
S1'

D40'

D24'

S5350'

D41'

D44'

S3'

Sub Line (Green)

S2'
S1'

D40'

D24'

S5350

D41

D44

S3

Main Line (Red)

S2
S1

D40

D24

S5350'

D41'

D44'

S3'

Sub Line (Red)

S2'
S1'

D40'

D24'

Driver

Driver

Driver

Driver

Driver

Driver

Driver

Driver

1

2

3

4

5

6

9

10

11

12

13

14

15

17

20

21

22

23

24

φSHUT

-B

φSHUT-G

φSHUT-R

φROG

V

OUT-R

VOUT-G

VOUT-B

φ1GND GND φRS φ3 φ2L

φ2φ1L'φ1Lφ4V

DDVDD

Block Diagram

Note) D24 and D24' are the start pixels for the optical black of Main Line and Sub Line. (These are not pixels immediately before multiplex.)

– 3 –

ILX128MA

Unit

pF
pF
pF
pF
pF
pF

Max.

—
—
—
—
—
—

Typ.

1530

20
20
20
10
10

Min.

—
—
—
—
—
—

Symbol
Cφ1, Cφ2
Cφ1L, Cφ1L', Cφ2L
Cφ3, Cφ4
CφRS
CφROG
CφSHUT

Item
Input capacity of φ1, φ2
Input capacity of φ1L, φ1L', φ2L
Input capacity of φ3, φ4
Input capacity of φRS
Input capacity of φROG
Input capacity of φSHUT

∗1

Input Pin Capacity

Unit

V

Max.

12.6

Typ.

12

Min.

11.4

Item

VDD

Recommended Supply Voltage

∗1

φSHUT represents φSHUT-R, φSHUT-G and φSHUT-B.

Pin Description

Pin
No.

Symbol Description

1
2
3
4
5
6
7
8

9
10
11
12

φ1L
φ1L'
φRS

VOUT-R
VOUT-G
VDD
NC
NC
GND

φ2
φSHUT-B
φSHUT-G

Clock pulse input
Clock pulse input
Clock pulse input
Signal output (red)
Signal output (green)
12V power supply
NC
NC
GND
Clock pulse input
Clock pulse input
Clock pulse input

Pin

No.

Symbol Description

13
14
15
16
17
18
19
20
21
22
23
24

φSHUT-R
φROG
φ1

NC
VDD
NC
NC
VOUT-B
GND

φ3
φ2L
φ4

Clock pulse input
Clock pulse input
Clock pulse input
NC

∗

12V power supply
NC
NC
Signal output (blue)
GND
Clock pulse input
Clock pulse input
Clock pulse input

∗

Connecting to GND is recommended.

– 4 –

ILX128MA

Unit
MHz
MHz
MHz

Max.

3
6
6

Typ.

1
2
2

Min.

—
—
—

Symbol
fφ1, fφ2, fφ1L, fφ1L', fφ2L
fφ3, fφ4
fφRS

Item

φ1, φ2, φ1L, φ1L', φ2L
φ3, φ4
φRS

Clock Frequency

Unit

V
V
V
V

Max.

5.25

0.1

5.25

0.5

Typ.

5.0
—

5.0
—

Min.

4.75
0

4.75
0

High level
Low level
High leve
Low level

φ1L, φ1L', φ2L, φ3, φ4

φ1, φ2, φRS, φROG, φSHUT

Input Clock Voltage Condition

Item

Unit

V/(lx · s)

%
%

V

lx · s

mV
mV

%

mA

%

Ω

V

mV

—

Remarks

Note 2

Note 3
Note 4
Note 5
Note 6

Note 7

Note 8
Note 9

Note 10

—
—

—
Note 11
Note 12
Note 13

Max.

2.47

5.59

3.38
15
15
—
—
—
—
—

2.0

5.0
—
50
—
—

7.7

200

—

Typ.

1.9

4.3

2.6
4
4
3

—

1.6

0.7

1.2

0.3

1.5

0.02
32
98

250

6.2
40

10000

Min.

1.33

3.01

1.82
—
—

2

2 × SEmin

0.8

0.4

0.6
—
—
—
—
92
—

4.7
—

1000

Symbol
RR
RG
RB
PRNU
PDF
VSAT
OE
SER
SEG
SEB
VDRK
DSNU
IL
IVDD
TTE
ZO
VOS
∆VOS
DR

Item

Red
Green
Blue

Red
Green
Blue

Electrooptical Characteristics (Note 1) (Ta = 25°C, VDD = 12V, fφRS = 2MHz, Input clock = 5Vp-p,

Light source = 3200K, IR cut filter CM-500S (t = 1mm))

Note)

1. For each color, the black level of Main Line is defined as the average value of D24, D25 to D39, and the
black level of Sub Line is defined as the average value of D24', D25' to D39'. The following electrooptical
characteristics signal processing is performed.

2. For the sensitivity test light is applied with a uniform intensity of illumination.

3. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)

PRNU = × 100 [%]

Where the maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the
average output to VAVE.

4. PDF = (∆VMAX/VAVE) × 100 [%]
Here, VAVE is defined as the average output, and ∆VMAX, the maximum value of ∆Vi in the range of the
following pixel.
Red, green, blue pixel arrangement PDF is when i = 1 to 5349. However, the definition of ∆Vi is as follows.

∆Vi = ABS {VOUT (i) – VOUT (i + 1)}

VOUT (i) is signal output of an effective pixel (i pixel) and VOUT (i + 1) is of the adjacent pixel (i + 1 pixel).

(VMAX – VMIN)/2

VAVE

Sensitivity

Sensitivity nonuniformity
Adjacent pixel difference
Saturation output voltage
Overflow exposure

Saturation exposure

Dark voltage average
Dark signal nonuniformity
Image lag
Current consumption
Total transfer efficiency
Output impedance
Offset level
Offset level difference
Dynamic range

– 5 –

ILX128MA

– 6 –

ILX128MA

5. Specifies at the minimum value of the saturation output voltage.

6. SEmin is the exposure at the minimum value (2V) of the saturation output voltage.

7. Saturation exposure is defined as in the right figure. SE = VSAT/R

8. For each color, Main Line is defined by the difference between the average value of D2 to D22 dummy
signal during no incident light and of D24 to D40, S1 to S5350. Sub Line is defined by the difference
between the average value of D2' to D22' dummy signal during no incident light and of D24' to D40', S1' to
S5350'.
Optical signal integration time τint stands at 10ms.

9. For each color, calculate the difference as follows; the maximum and minimum values of the dark output
voltage of respective Main Line and Sub Line; the dark voltage average value of respective Main Line and
Sub Line. Then, the highest value is defined as dark signal nonuniformity.
Optical signal integration time τint stands at 10ms.

10. VOUT = 500mV (Typ.)

11. Vos is defined as the output DC value when φRS is high.

12. For each color, the Main Line offset level of the optical black pixel is defined as Vos-main, the Sub Line
offset level, Vos-sub. Then, the offset level difference is defined as indicated below.

∆VOS = | VOS-main – VOS-sub |

φ1L and φ1L' are set to the same clock input.

13. Dynamic range is defined as follows.

DR = VSAT/VDRK
When the optical signal integration time is shorter, the dynamic range gets wider because the optical
signal integration time is in proportion to the dark voltage.

∆Vos

– 7 –

ILX128MA

Clock Timing Chart 1

Note) The transfer pulse φ1, φ2, φ1L, φ1L' and φ2L must have more than 5394 cycles.

φ3 and φ4 must have more than 10788 cycles.

5

0

φ3

5

0

φROG

5

0

φ2, φ2L

5

1

2

1

2

3

4

0

φ1, φ1L

φ1L'

5

0

φRS

5

0

φ4

VOUT

D1

D1'

D2

D23

D23'

D24

D24'

D40

D40'

S1

S1'

S5349'

S5350

S5350'

D41

D43'

D44

D44'

D41'

Optical black (16 pixels × 2)

Dummy signal (30 pixels + 25 pixels × 2) Effective pixel signal

(5350 pixels × 2)

Dummy signal

(4 pixels × 2)

1-line output period (5394 pixels × 2)

– 8 –

ILX128MA

Clock Timing Chart 2 (shutter operation)

5

0

φ3

5

0

φROG

5

0

φ2, φ2L

5

1

2

1

2

3

4

0

φ1, φ1L

φ1L'

5

0

φRS

5

0

φ4

5

0

φSHUT

Integration time

Note) Shutter pulse must not be high to low level or low to high level during effective pixel period.

– 9 –

ILX128MA

Clock Timing Chart 3

t5

t7

t6

φROG

φ1

φ2

t3

t4

t6

t7

t1

t2

φ1 and φ2 Cross Point

1.5V or more 1.5V or more

5V

0V

φ1

φ2

φ3 and φ4 Cross Point

1.5V or more 1.5V or more

5V

0V

φ3

φ4

Clock Timing Chart 4









φ1

φ2

t7

t6

t6

t7

φ1L
φ1L'

φ2L

φ3

φ4

φRS

V

OUT

t9

t11

t17

t10

t10

t18

t19

t8

t8

t9

t15

t16

t11

t12

Main Line Sub Line

t13

t14

t22

t21 t20

– 10 –

ILX128MA

Clock Pulse Recommended Timing

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Max.

—
—
—
10
10
60
60

30

∗1

30

∗1

30

∗1

30

∗1

30

∗1

30

∗1

—
—
—
—
—
—
—
—
—

Typ.

100
1500
1500

5

5
20
20
10
10
10
10
10
10

250

∗1

40

210

∗1

125

∗1

250
250

35

8
35

Min.

50
1200
1200

0
0
0
0
0
0
0
0
0

0
20
35
35
50
35
35
—
—
—

Symbol

t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22

Item

φROG, φ1 pulse timing
φROG pulse high level period
φROG, φ1 pulse timing
φROG pulse rise time
φROG pulse fall time
φ1 pulse rise/φ2 pulse fall time
φ1 pulse fall/φ2 pulse rise time
φ1L, φ1L' pulse rise/φ2L pulse fall time
φ1L, φ1L' pulse fall/φ2L pulse rise time
φ3 pulse rise/φ4 pulse fall time
φ3 pulse fall/φ4 pulse rise time
φRS pulse rise time
φRS pulse fall time
φRS pulse high level period
φ1L', φ2L – φ3, φ4 pulse timing 1
φ1L', φ2L – φ3, φ4 pulse timing 2
φRS, φ3 pulse timing

φ3, φ4 pulse low level period

Signal output delay time

The recommended duty of φ1, φ2, φ1L, φ2L, φ3 and φ4 = 50%.

∗1

These timing is the recommended condition under fφRS = 2MHz.

– 11 –

ILX128MA

Application Circuit

∗1

∗1

Data rate fφRS = 2MHz

1

2

3

4 5 6

7

8 9 10

11 12

13

24 23 22

21 20 19 18 17 16 15 14

φSHUT-R

IC1 IC2

IC1: 74AC04
IC2: 74HC04
Tr1: 2SC2785

φ4

φ2L

GND

φ3

V

OUT-B

NC

NC

V

DD

NC

φ1

φROG

φSHUT

-G

φ1L

φ1L'

φRS

V

OUT-R

VOUT-G

VDD

NC

NC

GND

φ2

φSHUT-B

10Ω

10Ω

φ4

IC2

2Ω

φ2

φSHUT

-B

100Ω

φSHUT-G

IC2

12V

47µF/
16V

0.1µF

φRS

10Ω

10Ω

φ2L

10Ω

φ3

5.1kΩ
V

OUT-B

Tr1

5.1kΩ

10Ω

Tr1

VOUT-G

5.1kΩ

10Ω

VOUT-R

Tr1

φ1L'

10Ω

φ1L

10Ω

100Ω

IC1 IC2

2Ω

φ1

φROG

100Ω

φSHUT-R

100Ω

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 12 –

ILX128MA

Example of Representative Characteristics (VDD = 12V, Ta = 25°C)

Wavelength [nm]

Relative sensitivity

550 600 650

400

0

0.2

0.4

0.6

0.8

1

450

500 700

Spectral sensitivity characteristics

(Standard characteristics)

Dark signal output temperature characteristics

(Standard characteristics)

Ta – Ambient temperature [°C]

Output voltage rate

30 40 500

0.1

0.5

1

5

10

10 20 60

Offset level vs. temperature characteristics

(Standard characteristics)

Ta – Ambient temperature [°C]

Vos – Offset level [V]

30 40 500

0

4

2

6

8

10

12

10 20 60

Offset level vs. VDD characteristics

(Standard characteristics)

VDD [V]

Vos – Offset level [V]

1211.4

0

4

2

6

8

12

10

12.6

Integration time output voltage characteristics

(Standard characteristics)

τ int – Integration time [ms]

Output voltage rate

51

0.1

0.5

1

10

Ta = 25°C

∆Vos
∆V

DD

0.1≈

∆Vos

∆Ta

8mV/°C≈

– 13 –

ILX128MA

Notes on Handling

1. Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive

shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Notes on Handling CCD Packages
The following points should be observed when handling and installing plastic packages.
a) Remain within the following limits when applying static load to the package.

(1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter

of the glass portion.)
(2) Shearing strength: 29N/surface
(3) Tensile strength: 29N/surface
(4) Torsional strength: 0.9Nm

b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be

generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.

c) Be aware that any of the following can cause the package to crack or dust to be generated.

(1) Applying repetitive bending stress to the external leads.
(2) Applying heat to the external leads for an extended period of time with soldering iron.
(3) Rapid cooling or heating.
(4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer.
(5) Applying the metal a crash or a rub against the plastic portion.

Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
d) The notch of the plastic portion is used for directional index, and that can not be used for reference of

fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap
with the notch of the plastic portion.

3. Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount,

cool sufficiently.

c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering

tool, ground the controller. For the temperature control system, use a zero-cross type.

Plastic portion

Cover glass

39N

Ceramic portion

Adhesive

(1)

29N

(3)

0.9Nm

(4)

29N

(2)

,

– 14 –

ILX128MA

4. Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch mirror surfaces by hand or have any object come in contact with mirror surfaces.

Should dirt stick to a mirror surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the mirror surfaces are grease stained. Be careful not to

scratch the mirror surfaces.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation on the mirror surfaces,

preheat or precool when moving to a room with great temperature differences.

5. Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.

6. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 15 –

ILX128MA

Package Outline Unit: mm

M

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

DRAWING NUMBER

Plastic-Ceramic

GOLD PLATING

5.43g

42ALLOY

1

24

12

13

H

V

3.58

10.16

0.25

0.461.778

5.334

24pin SDIP(400mil)

0˚ to 9˚

10.0 ± 0.3

55.7 ± 0.3

42.8(8µmX5350pixels)

No.1Pixel (Green(main line))

7.6 ± 0.3

5.0 ± 0.3

4.0 ± 0.5

4.28 ± 0.5

0.3

LS-B27(E)

1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm.

2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5.

Sony Corporation