Page 1
3000-pixel CCD Linear Image Sensor (B/W)
Description
The ILX103A is a rectangular reduction type CCD
linear image sensor designed for bar code POS
hand scanner and optical measuring equipment use.
A built-in timing generator and clock-drivers ensure
single 5V power supply for easy use.
Features
• Number of effective pixels: 3000 pixels
• Pixel size: 7µm × 200µm (7µm pitch)
• S/H output
• Built-in timing generator and clock-drivers
• Output amplifier gain switching function
(2-level: switching gain ratio 1:4)
• SIP small package
• Clock frequency: 500kHz (Typ.),
100kHz (Min.), 1MHz (Max.)
Absolute Maximum Ratings
• Supply voltage VDD 6V
•Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
Internal Structure
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E98X48A91-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ILX103A
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
VDD
GND
Vout
Vgg
φCLK
SWG
NC
NC
φROG
φSHUT
GND
V
DD
T1
V
DD
GND
NC
3000
Vgg
GND
V
DD
VDD
GND
VDD
GND
D24
D25
D54
D55
S1
S2
S3
S2999
S3000
D56
D65
Output Amplifier
Driver
Readout gate
Readout gate
CCD analog shift register
CCD analog shift register
Driver
Readout gate pulse
generator
Shutter pulse
generator
Timing generator
4
2
1 12 11 14 15
6 13 5 9 10
φSHUT
φROG
φCLK
T1
SWG
Vout
3
16 pin SIP (Ceramic)
Page 2
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ILX103A
Pin Description
Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
GND
Vout
Vgg
φCLK
SWG
NC
NC
φROG
φSHUT
GND
VDD
T1
VDD
GND
NC
Power supply
GND
Signal output
Output circuit gate bias
Clock pulse input
Control (Output circuit amplification factor ×4/×1)
NC
NC
Readout gate pulse input
Electrical shutter pulse input
GND
Power supply
TEST (Connect to GND with 1000pF capacitor)
Power supply
GND
NC
Recommended Voltage
Item
VDD
Min.
4.5
Mode Description
Output circuit gain
High
Low
Pin 6 SWG
VDD
GND
Typ.
5.0
Max.
5.5
Unit
V
Input Pin Capacity
Symbol
CφCLK
CφROG
CφSHUT
Min.
—
—
—
Typ.
10
10
10
Max.
—
—
—
Unit
pF
pF
pF
Item
Input capacity of φCLK pin
Input capacity of φROG pin
Input capacity of φSHUT pin
Page 3
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ILX103A
Electro-optical Characteristics (Analog Characteristic) (Note 1)
Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K,
IR cut filter: CM-500S (t = 1.0mm), Output circuit gain low mode
Item Symbol Min. Typ. Max. Unit Remarks
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
5V current consumption
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD
TTE
ZO
VOS
52.5
—
—
0.6
—
—
—
—
—
—
92.0
—
—
75
925
5.0
0.8
2.5
5.0
5.0
320
0.01
7.0
97.0
250
2.5
97.5
—
10.0
—
6.0
12.0
—
—
—
17.0
—
—
—
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
%
Ω
V
Note 2
Note 3
Note 4
—
Note 5
Note 6
Note 7
Note 8
Note 9
—
—
—
Note 10
Note)
1. In accordance with the given electro-optical characteristics, the even black level is defined as the average
value of D24, D25 to D53.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. Light source: LED λ = 660nm
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
PRNU = × 100 [%]
The maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the average
output to VAVE.
5. Integration time is 10ms.
6. The difference between the maximum and average values and the difference between the minimum and
average values of the dark output voltage is calculated. The larger value is defined as dark signal
nonuniformity. Integration time is 10ms.
7. Typical value is used for clock pulse and readout pulse. VOUT = 500mV.
8. DR = VSAT/VDRK
When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in
proportion to optical integration time.
9. SE = VSAT/R1
10. Vos is defined as indicated below.
(VMAX – VMIN)/2
VAVE
D51 D52
Vout
V
OS
GND
D53 D54 D55 S1
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ILX103A
–1
D1
D0
5
0
5
0
5
φROG
φSHUT
φCLK
V
OUT
Optical
black
(30 pixels)
Dummy signal (55 pixels)
1-Line output period (3066 pixels)
3100 or more clock pulses are required.
Effective picture
elements signal
(3000 pixels)
Dummy signal
(10 pixels)
0
D2
D3
D4
D21
D22
D23
D24
0
1
2
D53
D54
D55
S1
S2
S3
S4
S2998
S2997
S2999
S3000
D56
D57
D58
D59
D61
D60
D62
D63
D64
D65
Clock Timing Diagram
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ILX103A
Input Clock Voltage Condition
Min.
3.0
0.0
Typ.
VDD
—
Max.
5.5
0.1
Unit
V
V
Item
VIH
VIL
Symbol
t1, t2
—
Min.
0
40
Typ.
10
50
Max.
100
60
Unit
ns
%
Item
φCLK pulse rise/fall time
φCLK pulse Duty
∗1
Symbol
t5
t9
t6, t8
t7
Min.
1/8τ
1/8τ
0
6τ
Typ.
1/4τ
1/4τ
10
10τ
Max.
3/8τ
3/8τ
100
20τ
Unit
ns
ns
ns
ns
Item
φROG, φCLK pulse timing 1
φROG, φCLK pulse timing 2
φROG pulse rise/fall time
φROG pulse period
∗
This is applied to the all external pulses.
(φCLK, φROG, φSHUT)
φCLK Timing (For all modes)
t1
t3 t4
t2
φCLK
∗1
100 × t4/ (t3 + t4)
φROG, φCLK Timing
t6 t7 t8
φROG
φCLK
t9t5
Note) τ is the period of φCLK.
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ILX103A
φSHUT, φCLK Timing
Symbol
t11, t13
t12
t14
t15
Min.
0
4000
150
150
Typ.
10
5000
200
200
Max.
100
—
250
250
Unit
ns
ns
ns
ns
Item
φSHUT pulse rise/fall time
φSHUT pulse period
φSHUT, φCLK pulse timing 1
φSHUT, φCLK pulse timing 2
φSHUT
φCLK
t11 t12 t13
t15
t14
Symbol
t16
Min.
—
Typ.
230
Max.
—
Unit
ns
Item
φCLK-Vout output delay time1
φCLK
Vout
t16
∗2
∗1
fck = 500kHz, φCLK Duty = 50%, φCLK rise/fall time = 10ns
∗2
is data period.
φCLK Output Signal Timing
∗1
Note) The high periods of φROG and φSHUT are separated for 10τ or more.
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ILX103A
Application Circuit (Output gain low mode)
∗1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD
3kΩ
1µ/16V
0.01µ
1000p
22µ/10V
φCLK φROG φSHUT
5V
2SA1175
Signal output
GND
Vout
Vgg
φCLK
SWG
NC
NC
φROG
φSHUT
GND
VDDT1
VDDGND
NC
∗
2
∗1
This circuit diagram is the case when output circuit gain is low.
∗2
Connect T1 (Pin 13) to GND with 1000pF capacitor.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 8
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ILX103A
Example of Representative Characteristics (VDD = 5V, Ta = 25°C)
10
9
8
7
6
5
4
3
2
1
0
400 500 600 700
Wavelength [nm]
Spectral sensitivity characteristics (Standard characteristics)
Relative sensitivity
800 900 1000
10
5
1
0.5
0.1
0.05
0.01
–10 0 10 20
Ta – Ambient temperature [°C]
Output voltage vs. Temperature characteristics (Standard characteristics)
Output voltage rate
30 40 50 60
Page 9
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ILX103A
5
4
3
2
1
0
–10
0 10 20
Ta – Ambient temperature [°C]
Offset level vs. Temperature characteristics
(Standard characteristics)
VOS – Offset level [V]
30 40 50 60
∆Vos
∆Ta
~
–
–2.1mV/°C
5
4
3
2
1
0
4.5
V
DD [V]
Offset level vs. VDD characteristics
(Standard characteristics)
VOS – Offset level [V]
5 5.5
∆Vos
∆V
DD
~
–
0.49
Ta = 25°C
14
10
12
8
6
4
2
0
4.5
5
V
DD [V]
Supply current vs. VDD characteristics
(Standard characteristics)
IVDD – Supply current [mA]
5.5
Ta = 25°C
10
5
1
10
τ – Integration time [ms]
Output voltage vs. Integration time
(Standard characteristics)
Output voltage rate
50 100
Page 10
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ILX103A
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive
shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Notes on Handling CCD Cer-SIP Packages
The following points should be observed when handling and installing cer-SIP packages.
a) Remain within the following limits when applying static load to the ceramic portion of the package:
(1)Compressive strength:39N/surface (Do not apply load more than 0.5mm inside the outer perimeter of
the glass portion.)
(2)Shearing strength: 29N/surface
(3)Tensile strength: 29N/surface
(4)Torsional strength: 0.9Nm
b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be
generated and the package may fracture, etc., depending on the flatness of the ceramic portion.
Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive.
c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic
layers are shielded by low-melting glass,
(1)Applying repetitive bending stress to the external leads.
(2)Applying heat to the external leads for an extended period of time with a soldering iron.
(3)Rapid cooling or heating.
(4)Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as
tweezers.
(5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass.
Note that the preceding notes should also be observed when removing a component from a board after it
has already been soldered.
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering
tool, ground the controller. For the control system, use a zero cross type.
Upper ceramic layer 39N
Lower ceramic layer
Low-melting glass
(1)
29N
(3)
0.9Nm
(4)
29N
(2)
Page 11
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ILX103A
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch
the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
7) Normal output signal is not obtained immediately after device switch on.
Page 12
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ILX103A
Package Outline Unit: mm
1. The height from the bottom to the sensor surface is 1.6 ± 0.3mm.
2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
16pin SIP
30.3 ± 0.3
21.0 (7µm × 3000Pixels)
No.1 Pixel
1
16
H
V
5.08
0.4
1.27
4.65 ± 0.8
2.23 ± 0.3
4.0
4.2
5.0 ± 0.2
3.2 ± 0.5
2.4
0.25
1.325 ± 0.3
0.3
M
Cer-SIP
TIN PLATING
42 ALLOY
1.3g
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
LS-D4(E)
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