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IFPA300, IFPA301
Monolithic JFET Preamplifier
Description & Features
The IFPA300 series is an inverting transimpedance
amplifier featuring extremely low noise and a wide
gain-bandwidth suitable as a charge-sensitive preamplifier for a broad range of applications.
The monolithic IFPA300 series contain 8 n-channel
epitaxial-channel diffused-gate JFETs to achieve
optimally low 1/f noise performance over a wide
temperature range (120K-300K).
DC open loop gain 85 dB
GBW 200 MHz
¯eN@ 10 Hz 3.0 nV/√Hz
General Specifications
Power Dissipation at VDD = 12 V <100 mW
Input Leakage Current (T = 300 K) 10 pA
Input-Referred Noise Voltage (f = 10 kHz) 0.6 nV/√Hz
Input-Referred Noise Voltage (f = 10 Hz) 3.0 nV/√Hz
Output Range at VDD = 12 V 4.0 V (5.0 V Max)
Designed to drive 50Ω load.
Charge Sensitive
Preamplifier Specifications
The IFPA300 Series is actually tailored to detector
capacitance in the 100 Ð 1000 pF range.
Input Open-Loop Capacitance 60 pF
Rise Time (CD = 500 pF, Cf = 33 pF) 20 ns
Equivalent Noise Charge
Absolute maximum ratings at TA = 25°C
All pins (except Input) referenced to Bias 3 85 dB
Input to Bias 3 Ø V
Power Dissipation 225 mW
Derating Factor 1.8 mW/°C
Operating Temperature 150°C
At this time, there are two units in this family.
The 300/301 Series gives more flexibility with respect
to output transistor drain.
The 310/311 Series ties the output transistor drain to
DD
line.
Simplified Schematic Circuit
J
4
J
7
J
3
V
DD
Substrate
the V
Open
Drain
8
Output
Open
Bias 1
Bias 2
J
J
2
J
6
Source
Input
J
1
J
5
Output
(Measured with semigaussian shaping, peaking
time = t
4200 e– rms at CD @ 500 pF, tp= 0.2 µm
3200 e– rms at CD @ 500 pF, tp= 1.0 µm
4200 e– rms at CD @ 500 pF, tp= 4.0 µm
)
p
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287 FAX (972) 276-3375
Bias 3
Packages & Test Circuit Overside
V
SS
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Test Point #
Test Point #2
DUT
J
5
J
6
J
7
J
1
J
2
J
3
J
4
J
8
V
SS
V
DD
VDD = +12 V
– Vsupply = – 6 V
Open
Substrate
Source
Output
Open
Drain
Output
120K
20K
10KΩ
Bias 1
Bias 2
Bias 3
Input
2MΩ
1MΩ
AC
Input
10pF
10pF
0.009 (0.23)
0.007 (0.18)
45°
0.022 (0.56)
0.018 (0.046
0.158 (4.01)
0.150 (3.81)
0.244 (6.20)
0.228 (5.79)
0.028 (0.71)
0.024 (0.61)
0.050 (1.27)
0.015 (0.37)
Min.
0.018 (0.46
0.014 (0.36)
0.197 (5.00)
0.188 (4.78)
0.049 (1.24)
0.059 (1.50)
0.069 (1.75)
0.053 (1.35)
56
Top
78
4321
45°
6
2
31
48
57
0.010 (0.25)
0.040 (1.02)
Bottom View
8 Leads - Dia.
0.016 (0.41)
0.021 (0.53)
0.335 (8.51)
0.370 (9.40)
0.110 (2.79)
0.160 (4.06)
0.500 (12.70)
0.305 (7.75)
0.335 (8.51)
0.028 (0.71)
0.034 (0.86)
0.200 (5.08)
Basic
0.029 (0.74)
0.045 (1.14)
0.010 (0.25)
0.040 (1.02)
Standoff
0.165 (4.19)
0.185 (4.70)
IFPA300, IFPA301
Monolithic JFET Preamplifier
Input FET J1 selected to the
following elecrical parameters.
Parameter Conditions Min Max Units
BV
GSS
I
GSS
I
DSS
V
GS(OFF)
G
M
V
GSF
Parameter Conditions Min Max Units
VDCout Vdd = 12 V, – VS = – 6 V 6 10 V
Vin Vdd = 12 V, – VS = – 6 V – 0.6 – 1.6 V
VACout Vdd = 12 V, – VS = – 6 V 50 mV
VACout Vdd = 12 V, – VS = – 6 V 20 mV
Vds = 0, Ig = 1 µA – 25 Volts
Vds = 0, Vgs = – 10 V 2 nA
Vds = 0, Vgs = 10 V 40 500 mA
Vds = 0, Id = 1 µA 1 2 Volts
Vgs = 0, Vds = 10 V 50 mM
Id = 1 µA 0.35 0.65 Volts
Test Circuit Reference
Test pt #1
Test pt #2
t = O µsec
t = 100 µsec
IFPA300 uses TO-99 Package
Dimensions in Inches (mm)
Pin Configuration
1 Bias 3, 2 VSS, 3 Bias 1, 4 VDD /Substrate
5 Open Drain Output, 6 Open Source Output, 7 Bias 2, 8 Input
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IFPA301 uses SOIC-8 Package
Dimensions in Inches (mm)
Pin Configuration
1 Bias 2, 2 Input, 3 Bias 3, 4 VSS, 5 Bias 1, 6 VDD/Substrate
7 Open Drain Output, 8 Open Source Output
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287 FAX (972) 276-3375
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