Datasheet IDT7MP4095S20Z, IDT7MP4095S20M, IDT7MP4095S15Z, IDT7MP4095S15M, IDT7MP4060S20Z Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

128K x 32
CMOS STA TIC RAM
MODULES

IDT7MP4060
IDT7MP4095

FEATURES:

• High density 4 megabit static RAM modules

• Low profile 64-pin ZIP (Zig-zag In-line vertical Package),
64-lead, 72-lead SIMMs (Single In-line Memory Modules)

• Fast access time: 15ns (max.)

• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate

• Single 5V (±10%) power supply

• Multiple GND pins and decoupling capacitors for maxi­mum noise immunity

• Inputs/outputs directly TTL compatible

• Gold plated fingers on the SIMM version

PIN CONFIGURATION – 7MP4095

PD
I/O
I/O
I/O
I/O
V

CC

A
A

A
I/O
I/O
I/O
I/O

WE

A

CS
CS

A
GND
I/O
I/O
I/O
I/O

A

A

A

A
I/O
I/O
I/O
I/O
GND

GND

11
13
15
17
19
21
23
25
27
29
31

33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63

1

PD

3

I/O

5

I/O

7

I/O

9

I/O
A

0

A

1

A

2

I/O
I/O
I/O
I/O
GND
A

15

CS

CS

NC

OE

I/O
I/O
I/O
I/O
A

3

A

4

A

5

V

CC

A

6

I/O
I/O
I/O
I/O

2

0

4

0

6

1

8

2

10

3

12
14

7

16

8

18

9

20

4

22

5

24

6

26

7

28
30

14

32

1
3

34

16

36
38

16

40

17

42

18

44

19

46

10

48

11

50

12

52

13

54

20

56

21

58

22

60

23

62
64

ZIP, SIMM

TOP VIEW

1
8
9
10
11

12
13
14
15

2

4

24
25
26
27

28
29
30
31

PD0 - OPEN
PD

1

- OPEN

DESCRIPTION:

The IDT7MP4095/7MP4060 are 128K x 32 static RAM
modules constructed on an epoxy laminate (FR-4) substrate
using four 128K x 8 static RAMs in plastic SOJ packages. The
IDT7MP4095/7MP4060 are available with access times as
fast as 15ns with minimal power consumption.

The IDT7MP4095 is packaged in a 64-pin FR-4 ZIP (Zig­zag In-line vertical Package) or a 64-lead SIMM (Single In-line
Memory Module). The IDT7MP4060 is packaged in a 72-lead
SIMM. The ZIP configuration allows 64 pins to be placed on
a package 3.65 inches long and 0.21 inches thick. At only 0.60
inches high, this low-profile package is ideal for systems with
minimum board spacing, while the SIMM configuration allows
use of edge mounted sockets to secure the module.

All inputs and outputs of the IDT7MP4095/7MP4060 are
TTL compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for opera­tion and provides equal access and cycle times for ease of
use.

FUNCTIONAL BLOCK DIAGRAM

4

8

3147 drw 01

ADDRESS

WE

OE

17

CS

1

8

CS

CS

2

128K x 32

RAM

8 8

I/O

0-31

CS

3

PIN NAMES

I/O0–31 Data Inputs/Outputs
A0–16 Addresses

CS

1–4 Chip Selects

WE
OE

VCC Power
GND Ground
NC No Connect

Write Enable
Output Enable

3147 tbl 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE SEPTEMBER 1996

1996 Integrated Device Technology, Inc. DSC-3147/7

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

7.09 1

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION – 7MP4060

NC

SIMM

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35

37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

PD
GND
PD
I/O

8

I/O

9

I/O

10

I/O

11

A

0

A

1

A

2

I/O

12

I/O

13

I/O

14

I/O

15

GND

15

A

CS

2

CS

4

NC

OE

24

I/O
I/O

25

I/O

26

I/O

27

A

3

A

4

A

5

V

CC

A

6

I/O

28

I/O

29

I/O

30

I/O

31

NC
NC

2

1

NC
PD
PD

I/O
I/O
I/O
I/O
V

CC

A
A

A
I/O
I/O
I/O
I/O

WE

A

CS

CS

A

GND

I/O
I/O
I/O
I/O

A
A
A

A
I/O
I/O
I/O
I/O

GND

NC

NC

3
0
0
1
2
3

7
8
9
4
5
6
7

14

1

3

16

16
17
18
19
10
11
12
13
20
21
22
23

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36

38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

TOP VIEW

PD
PD
PD
PD

0

- OPEN

1

- OPEN

2

- OPEN

3

- GND

3147 drw 13

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol Parameter

IN(D) Input Capacitance V(IN) = 0V 12 pF

C

(Data and CS)

IN(A) Input Capacitance V(IN) = 0V 40 pF

C

(Address, WE, OE)

OUT Output Capacitance V(OUT) = 0V 12 pF

C

NOTE: 3147 tbl 04

1. This parameter is guaranteed by design but not tested.

(1)

Conditions Max. Unit

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — 5.8 V

IL Input Low Voltage –0.5

V

NOTE: 3147 tbl 05

1. VIL (min) = –3.0V for pulse width less than 10ns.

(1)

— 0.8 V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade Temperature GND VCC

Commercial 0°C to +70°C 0V 5.0V ± 10%

3147 tbl 06

TRUTH TABLE

Mode

Standby H X X High Z Standby
Read L L H DATAOUT Active
Write L X L DATAIN Active
Read L H H High-Z Active

CSCSOEOEWE

WE

Output Power

3147 tbl 02

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Value Unit

TERM Terminal Voltage with –0.5 to +7.0 V

V

Respect to GND
TA Operating Temperature 0 to +70 °C
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +125 °C

OUT DC Output Current 50 mA

I

NOTES: 3147 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

7.09 2

(1)

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0°C to +70°C)

Symbol Parameter Test Conditions Min. Max. Unit

LI| Input Leakage VCC = Max.; VIN = GND to VCC —10µA

|I

(Data and CS)

LI| Input Leakage VCC = Max.; VIN = GND to VCC —40µA

|I

(Address, WE, and OE)
|ILO| Output Leakage VCC = Max.; CS = VIH, VOUT = GND to VCC —10µA
VOL Output Low VCC = Min., IOL = 8mA — 0.4 V

OH Output High VCC = Min., IOH = –4mA 2.4 — V

V

Symbol Parameter Test Conditions Max. Unit

CC Dymanic Operating f = fMAX;

I

Current VCC = Max.; Output Open

SB Standby Supply

I

CS

Current Outputs Open, f = fMAX

ISB1 Full Standby

CS

Supply Current V

CS

= VIL 760 mA

≥ VIH, VCC = Max. 160 mA

≥ VCC – 0.2V; f = 0 60 mA

IN > VCC – 0.2V or < 0.2V

3147 tbl 07

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figures 1 and 2

+5 V

480 Ω

DATA

OUT

255Ω

Figure 1. Output Load

30 pF*

* Includes scope and jig.

3147 tbl 08

DATA

OUT

+5 V

480 Ω

255Ω

Figure 2. Output Load

(for tOLZ, tOHZ, tCHZ, tCLZ,

tWHZ, tOW)

5 pF*

3147 drw 03

7.09 3

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(VCC = 5V ±10%, TA = 0°C to +70°C)

-15 -20
Symbol Parameter Min. Max. Min. Max. Unit
Read Cycle

tRC Read Cycle Time 15 — 20 — ns
tAA Address Access Time — 15 — 20 ns
tACS Chip Select Access Time — 15 — 20 ns

(1)

tCLZ
tOE Output Enable to Output Valid — 8 — 10 ns
tOLZ
tCHZ
tOHZ
tOH Output Hold from Address Change 3 — 3 — ns

(1)

tPU

(1)

tPD

Write Cycle

tWC Write Cycle Time 15 — 20 — ns
tCW Chip Select to End of Write 12 — 18 — ns
tAW Address Valid to End of Write 12 — 18 — ns
tAS Address Set-up Time 0 — 0 — ns
tWP Write Pulse Width 12 — 18 — ns
tWR Write Recovery Time 0 — 3 — ns
tWHZ
tDW Data to Write Time Overlap 10 — 12 — ns
tDH Data Hold from Write Time 0 — 0 — ns

OW

t

NOTE: 3147 tbl 10

1. This parameter is guaranteed by design, but not tested.

Chip Select to Output in Low Z 3 — 3 — ns

(1)

Output Enable to Output in Low Z 0 — 0 — ns

(1)

Chip Deselect to Output in High Z — 8 — 12 ns

(1)

Output Disable to Output in High Z — 8 — 12 ns

Chip Select to Power-Up Time 0 — 0 — ns
Chip Deselect to Power-Down Time — 15 — 20 ns

(1)

Write Enable to Output in High Z — 8 — 13 ns

(1)

Output Active from End of Write 3 — 3 — ns

7.09 4

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1

ADDRESS

OE

CS

t

ACS

(5)

t

CLZ

DATA

OUT

TIMING WAVEFORM OF READ CYCLE NO. 2

ADDRESS

t

OH

(1)

t

AA

(1,2,4)

t

AA

t

RC

t

CHZ

t

t

OHZ

(5)

OH

(5)

3147 drw 04

t

OH

t

OE

(5)

t

OLZ

t

RC

DATA

OUT

TIMING WAVEFORM OF READ CYCLE NO. 3

(1,3,4)

DATA VALIDPREVIOUS DATA VALID

CS

t

ACS

(5)

tCLZ

DATA OUT

NOTES:

1.WE is High for Read Cycle.

2. Device is continuously selected. CS = V

3. Address valid prior to or coincident with CS transition low.

4.OE = V

5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

IL.

IL.

tCHZ

3147 drw 05

(5)

3147 drw 06

7.09 5

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

tWC

ADDRESS

OE

tAW

CS

t

WP

(6)

WE

DATA OUT

DATA IN

tAS tWR

tWHZ

(6)

tOHZ

(4)

WEWE CONTROLLED TIMING)

(7)

(6)

tOW

tDH

tDW

DATA VALID

(1, 2, 3, 7)

(6)

tOHZ

(4)

3147 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

t

WC

CSCS CONTROLLED TIMING)

(1, 2, 3, 5)

ADDRESS

t

AW

CS

t

AS

t

CW

t

WR

WE

t

DW

DATA

IN

NOTES:

1.WE or CS must be high during all address transitions.

2. A write occurs during the overlap (t

WR is measured from the earlier of

3. t

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.

6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.

7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of t

WP) of a low

CS

or WE going high to the end of write cycle.

CS

and a low WE.

DATA VALID

t

DH

WP or (tWHZ + tDW).

3147 drw 08

7.09 6

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

PACKAGE DIMENSIONS – IDT7MP4095
SIMM VERSION

3.840

3.860

3.574

0.620

0.640

0.240

0.260

PIN 1

0.070

0.090

3.594

0.250
TYP.

FRONT VIEW

0.050
TYP.

0.390

0.410

0.210
MAX.

0.045

0.055

SIDE VIEW

ZIP VERSION

0.600
MAX.

PIN 1

0.015

0.025

BACK VIEW

0.250
TYP.

0.060

0.064

3.640

3.660

FRONT VIEW

0.100
TYP.

0.050
TYP.

PIN 1

0.125

0.175

0.062 R

3147 drw 09

0.210
MAX.

0.100
TYP.

SIDE VIEW

BACK VIEW

3147 drw 10

7.09 7

IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES COMMERCIAL TEMPERATURE RANGE

PACKAGE DIMENSIONS – IDT7MP4060

FRONT VIEW

SIDE VIEW

0.640

0.660

0.240

0.260

0.070

0.090

PIN 1

4.240

4.260

0.250 TYP

0.060

R

0.064

BACK VIEW

3.974

3.994

0.050 TYP

0.390

0.410

PIN 1

0.210 MAX

0.045

0.055

0.062 R

3147 drw 11

ORDERING INFORMATION

IDT

XXXXX
Device

Type

X

PowerXSpeedXPackage

X

Process/

Temperature

Range

Blank

M
Z

Commercial (0°C to +70°C)

FR-4 SIMM (Single In-line Memory Module)
FR-4 ZIP (Zig-zag In-line Package)

15
20

Speed in Nanoseconds

S Standard Power

IDT7MP4060
IDT7MP4095

128K x 32 Static RAM Module (SIMM only)
128K x 32 Static RAM Module

3147 drw 12

7.09 8