• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163383/1632383 belong to IDT's family of Bus
switches. Bus switch devices perform the function of connecting or isolating two ports without providing any inherent
current sink or source capability. Thus they generate little or
FUNCTIONAL BLOCK DIAGRAM
A0
C0
no noise of their own while providing a low resistance path for
an external driver. These devices connect input and output
ports through an n-channel FET. When the gate-to-source
junction of this FET is adequately forward-biased the device
conducts and the resistance between input and output ports
is small. Without adequate bias on the gate-to-source junction
of the FET, the FET is turned off, therefore with no VCC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST1632xxx integrates terminating resistors in the
device, thus eliminating the need for external 25Ω series
resistors.
The FST163383 and FST1632383 each provide four 4-bit
TTL- compatible ports that support 2 way bus exchange. The
BX pin controls the bus exchange and the BE pin serves as the
enable pin.
A5
C5
B0
A4
B4
BX1
BE1
PIN DESCRIPTION
Pin NamesI/ODescription
A
0-9
, B
0-9
C
0-9
, D
0-9
BE
1,2
BX
1,2
I/OBuses A, B
I/OBuses C, D
IBus Switch Enable (Active LOW)
IBus Exchange
D0
C4
D4
3474 tbl 01
B5
A9
B9
BX2
BE2
D5
C9
D9
3474 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
VCC = Min. VIN = 0.0V163xxx—57Ω
ION = 30mA 1632xxx172840
VCC = Min. VIN = 2.4V163xxx—1015Ω
ION = 15mA 1632xxx203548
IOFFInput/Output Power Off LeakageVCC = 0V, VIN or VO≤ 4.5V——1µA
ICCQuiescent Power Supply CurrentVCC = Max., VIN = GND or VCC—0.13µA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Measured by voltage drop between ports at indicated current through the switch.
(2)
Max.Unit
3474 tbl 05
3
Page 4
IDT74FST163383, IDT74FST1632383
20-BIT BUS EXCHANGE SWITCHCOMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
SymbolParameterTest Conditions
∆ICCQuiescent Power Supply Current
TTL Inputs HIGH
ICCDDynamic Power Supply
(4)
Current
VCC = Max.
V
IN = 3.4V
(3)
VCC = Max.
Outputs Open
(1)
VIN = VCC
VIN = GND
Min. Typ.
—0.51.5mA
—3040µA/
Enable Pin Toggling
50% Duty Cycle
ICTotal Power Supply Current
(6)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—6.08.0mA
Enable Pins Toggling
(20 Switches Toggling)
fi = 10MHz
VIN = 3.4
V
IN = GND
—6.59.5
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fiN)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
N = Number of Switches Toggling at fi
All currents are in milliamps and all frequencies are in megahertz.
(2)
Max.Unit
MHz/
Switch
3474 tbl 06
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA =–40°C to +85°C, VCC = 5.0V ±10%
1633831632383
SymbolDescriptionCondition
tPLH
tPHL
Data Propagation Delay
Ai to Ci, Di Bi to Ci, Di
(3,4)
CL = 50pF
L = 500Ω
R
(1)
tBXSwitch Multiplex Delay
BX to Ai, Bi, Ci, Di
tPZH
tPZL
tPHZ
tPLZ
|QCI|Charge Injection, Typical
|QCDI|Charge Injection, Typical
NOTES:
1. See test circuit and waveforms.
2. Minimum limits guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant
for the switch alone is of the order of 2.5ns for 50pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals,
it adds very little propagation delay to the system. Propagation delay on the bus switch when used in a system is determined by the driving circuit on the
driving side of the switch and its interaction with the load on the driven side.
5. Measured at switch turn off, load = 50 pF in parallel with 10 MΩ scope probe, VIN = 0.0 volts.
6. Measured at switch turn off through bus multiplexer, (e.g.- A to C = >A to D), load = 50 pF in parallel with 10 MΩ scope probe, VIN at A = 0.0 volts. Charge
injection is reduced because the injection from the turn off of the A to C switch is compensated by the turn on of the B to C switch.
7. Characterized parameter. Not 100% tested.
Switch Turn on Delay
BE to Ai, Bi, Ci, Di
Switch Turn off Delay
BE to Ai, Bi
(3)
(5,7)
(6,7)
(2)
Min.
Typ.Max.Unit
——0.251.25ns
1.5—6.57.5ns
1.5—6.57.5ns
1.5—5.55.5ns
—1.5——pC
—0.5——
3474 tbl 07
4
Page 5
IDT74FST163383, IDT74FST1632383
20-BIT BUS EXCHANGE SWITCHCOMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
V
CC
V
OUT
Pulse
Generator
V
IN
D.U.T.
50pF
T
R
C L
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
500Ω
500Ω
7.0V
3474 lnk 03
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3474 lnk 04
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Open
PULSE WIDTH
LOW-HIGH-LOW
HIGH-LOW-HIGH
PULSE
tW
PULSE
3474 lnk 08
1.5V
1.5V
3474 lnk 05
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
tPLH
OUTPUT
tPLHtPHL
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
V
OH
1.5V
VOL
3V
1.5V
0V
3474 lnk 06
ENABLE AND DISABLE TIMES
ENABLEDISABLE
3V
CONTROL
INPUT
t
PLZtPZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
3.5V
1.5V
0.3V
tPZHtPHZ
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF≤ 2.5ns; tR≤ 2.5ns
SWITCH
OPEN
1.5V
0V
0.3V
1.5V
0V
3.5V
VOL
VOH
0V
3474 lnk 07
5
Page 6
IDT74FST163383, IDT74FST1632383
20-BIT BUS EXCHANGE SWITCHCOMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX
Temp. Range
FST
Device Type
16 XX
X
Package
PV
PA
PF
163383
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
20-Bit Bus Exchange Switch
1632383
74–40°C to +85°C
3474 drw 08
6
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