Datasheet IDT74FCT841DTSOB, IDT74FCT841DTQB, IDT74FCT841DTQ, IDT74FCT841DTPYB, IDT74FCT841DTPY Datasheet (Integrated Device Technology)

Integrated Device Technology, Inc.

FAST CMOS
BUS INTERFACE
LATCHES

IDT54/74FCT841AT/BT/CT/DT

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility

– VOH = 3.3V (typ.)

– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation

Enhanced versions
– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for FCT841T:

– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”

FUNCTIONAL BLOCK DIAGRAM

D0

D1

D2

D3

DESCRIPTION:

The FCT8xxT series is built using an advanced dual metal

CMOS technology.

The FCT8xxT bus interface latches are designed to elimi­nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high IOL/IOH.

All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capaci­tance bus loading in high-impedance state.

D4

D5

D8

D9

D

Q

LE

LE

OE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

D

Q

LE

0

Y

D

Q

LE

1

Y

D

Q

LE

2

Y

D

Q

LE

3

Y

D

Q

LE

4

Y

Y

D

Q

LE

5

D

Q

LE

8

Y

Y

9

2571 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996

1996 Integrated Device Technology, Inc. 6.22 2571/6

1

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES

PIN CONFIGURATIONS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OE

D
D1
D2
D3
D4
D5
D6
D7
D
D9

GND

VCC1

24

2

0

3

P24-1

4

D24-1

5

SO24-2

6

SO24-7

7

SO24-8

8

&

9

E24-1

10

8

11
12

23
22
21
20
19
18
17
16
15
14
13

Y
Y1
Y2
Y3
Y4
Y
Y6
Y7
Y8

Y9
LE

0

5

INDEX

D
D
D

NC

D
D
D

1

D

4

2

5

3

6

4

7
8

5

9

6

10

7

11

1213

8

D

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

2571 drw 02 2571 drw 03

PIN DESCRIPTION FUNCTION TABLE

Name I/O Description

DI I The latch data inputs.
LE I The latch enable input. The latches are

transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.

YI O The 3-state latch outputs.

OE

I The output enable control. When OE is

LOW, the outputs are enabled. When
is HIGH, the outputs V

are in high-

I

OE

impedance (off) state.

2571 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

TA Operating

Terminal Voltage
with Respect to
GND

–0.5 to

V

CC +0.5

–0.5 to

VCC +0.5

0 to +70 –55 to +125 °C

V

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C
Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C
Temperature

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

–60 to +120 –60 to +120 mA
Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed

CC by +0.5V unless otherwise noted.

V

2. Input and V

3. Outputs and I/O terminals only.

CC terminals only.

2571 lnk 03

OE

NOTE: 2571 tbl 02

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

COUT Output

NOTE:

1. This parameter is measured at characterization but not tested.

Inputs Internal Output

OE

LE DI QI YI Function

H H L L Z High Z
H H H H Z High Z
H L X NC Z Latched (High Z)

L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched

Capacitance

Capacitance

OE

NC

1

L28-1

CC

V

Y

Y

262728

25

Y

24

Y

23

Y
NC

22

Y

21

Y

20

Y

19

0

D

32

0

1

1817161514

NC

LE

9

8

Y

Y

9

D

GND

LCC

TOP VIEW

(1)

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

2
3
4

5
6
7

2571 lnk 04

6.22 2

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current
II L Input LOW Current

(4)

(4)

VI = 0.5V — — ±1

VCC = Max. VI = 2.7V — — ±1 µA

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA

(4)

(4)

VO = 0.5V — — ±1

VCC = Max., VI = VCC (Max.) — — ±1 µA

IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA

(2)

Max. Unit

2571 lnk 05

OUTPUT DRIVE CHARACTERISTICS FOR FCT841T

Symbol Parameter Test Conditions

V

OH

V

OL

I

OS

I

OFF

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

5. This parameter is guaranteed but not tested.

Output HIGH Voltage VCC = Min.

IN

= V

IH

or V

V

IL

Output LOW Voltage VCC = Min.

IN

= V

IH

or V

V

IL

Short Circuit Current VCC = Max., VO = GND
Input/Output Power Off Leakage

(5)

A = –55°C.

VCC = 0V, V

IN

or V

O

(3)

≤ 4.5V — —

(1)

IOH = –6mA MIL.

OH

= –8mA COM'L.

I
IOH = –12mA MIL.

OH

= –15mA COM'L.

I
I

OL

= 32mA MIL.

OL

= 48mA COM'L.

I

Min. Typ.

2.4 3.3 — V

2.0 3.0 — V

— 0.3 0.5 V

–60 –120 –225 mA

(2)

Max. Unit

±

1

µ

A

2571 lnk 06

6.22 3

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply Current

(4)

VCC = Max.
V

IN = 3.4V

VCC = Max.

(3)

Outputs Open

OE

= GND

(1)

VIN = VCC
VIN = GND

Min. Typ.

— 0.5 2.0 mA

— 0.15 0.25 mA/

LE = VCC
One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max. VIN = VCC — 1.5 3.5 mA
Outputs Open

VIN = GND

fi = 10MHz
50% Duty Cycle

OE

= GND

IN = 3.4

V
V

IN = GND

— 1.8 4.5

LE = VCC
One Bit Toggling
VCC = Max. VIN = VCC — 3.0 6.0

Outputs Open

VIN = GND
fi = 2.5MHz
50% Duty Cycle

OE

= GND

IN = 3.4

V

V

IN = GND

— 5.0 14.0

LE = VCC
Eight Bits Toggling

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT + IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D

T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

f

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

2571 tbl 07

6.22 4

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

(1)

(4)

Min.

1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 ns

1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0

Symbol Parameter Conditions

tPLH
tPHL

Propagation Delay

I to YI (LE = HIGH)

D

CL = 50pF

R

L = 500Ω

CL = 300pF

RL = 500Ω
tPLH
tPHL

Propagation Delay

I

LE to Y

CL = 50pF

R

L = 500Ω

CL = 300pF

(4)

1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 ns

1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0

RL = 500Ω
tPZH
tPZL

Output Enable Time OE to YI CL = 50pF

R

L = 500Ω

CL = 300pF

(4)

1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 ns

1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0

RL = 500Ω

L = 500Ω

(4)

1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 ns

1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5

tPHZ
tPLZ

Output Disable Time OE to Y I CL = 5pF

RL = 500Ω

CL = 50pF

R
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — ns

tH Data to LE Hold Time RL = 500Ω 2.5 — 3.0 — 2.5 — 2.5 — ns
tW LE Pulse Width HIGH

NOTES: 2571 tbl 08

1. See test circuit and waveforms. 3. These parameters are guaranteed but not tested.

2. Minimum limits are guaranteed but not tested on Propagation Delays. 4. These conditions are guaranteed but not tested.

(3)

4.0 — 5.0 — 4.0 — 4.0 — ns

FCT841AT FCT841BT

Com'l. Mil. Com'l. Mil.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max.

Unit

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT841CT FCT841DT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions

tPLH
tPHL

Propagation Delay

I to YI (LE = HIGH)

D

CL = 50pF

R

L = 500Ω

CL = 300pF

(1)

(4)

(2)

Min.

Max. Min.

1.5 5.5 1.5 6.3 1.5 4.2 — — ns

1.5 13.0 1.5 15.0 1.5 8.0 — —

RL = 500Ω
tPLH
tPHL

Propagation Delay

I

LE to Y

CL = 50pF

R

L = 500Ω

CL = 300pF

(4)

1.5 6.4 1.5 6.8 1.5 4.0 — — ns

1.5 15.0 1.5 16.0 1.5 8.0 — —

RL = 500Ω
tPZH
tPZL

Output Enable Time OE to YI CL = 50pF

R

L = 500Ω

CL = 300pF

(4)

1.5 6.5 1.5 7.3 1.5 4.8 — — ns

1.5 12.0 1.5 13.0 1.5 9.0 — —

RL = 500Ω

L = 500Ω

(4)

1.5 5.7 1.5 6.0 1.5 4.0 — — ns

1.5 6.0 1.5 6.3 1.5 4.0 — —

tPHZ
tPLZ

Output Disable Time OE to Y I CL = 5pF

RL = 500Ω

CL = 50pF

R
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 1.5 — — — ns

tH Data to LE Hold Time RL = 500Ω 2.5 — 2.5 — 1.0 — — — ns
tW LE Pulse Width HIGH

NOTES: 2571 tbl 09

1. See test circuit and waveforms. 3. These parameters are guaranteed but not tested.

2. Minimum limits are guaranteed but not tested on Propagation Delays. 4. These conditions are guaranteed but not tested.

(3)

4.0 — 4.0 — 3.0 — — — ns

(2)

Max. Min.

(2)

Max. Min.

(2)

Max.

Unit

6.22 5

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES

TEST CIRCUITS AND WAVEFORMS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS FOR ALL OUTPUTS

V

CC

7.0V

SWITCH POSITION

Test

Open Drain
Disable Low

Enable Low

All Other Tests

Generator.

Pulse

Generator

500

Ω

V

V

IN

OUT

D.U.T.

50pF

T

R

C

500

Ω

L

2571 drw 04

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C
R

T = Termination resistance: should be equal to ZOUT of the Pulse

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

t

REM

H

t

H

t

SU

t

SU

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

2571 drw 05

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

Switch

Closed

Open

2571 lnk 11

1.5V

t

W

1.5V

2571 drw 06

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

PLH

t

PLH

t

PHL

t

PHL

3V

1.5V
0V

V

OH

1.5V

V

OL

3V

1.5V
0V

2571 drw 07

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

t

PHZ

PLZ

t

F ≤ 2.5ns; tR ≤ 2.5ns

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

LOW

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

0.3V

0.3V

1.5V
0V

3.5V

V

OL

V

OH

0V

2571 drw 08

6.22 6

IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

FCT

XXXX

Device TypeXPackage

X

Process

Blank
B

P
D
E
L
SO
PY
Q

841AT
841BT
841CT
841DT

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package

10-Bit Non-Inverting Latch

–55°C to +125°C
0°C to +70°C

2571 drw 09

6.22 7