Datasheet IDT54FCT841A, IDT54FCT841B, IDT54FCT841C, IDT74FCT841A, IDT74FCT841B Datasheet (Integrated Device Technology)

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

Integrated Device Technology, Inc.

HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES

IDT54/74FCT841A/B/C

FEATURES:

• Equivalent to AMD’s Am29841-46 bipolar registers in
pinout/function, speed and output drive over full tem­perature and voltage supply extremes

• IDT54/74FCT841A equivalent to FAST speed

• IDT54/74FCT841B 25% faster than FAST

• IDT54/74FCT841C 40% faster than FAST

• Buffered common latch enable, clear and preset inputs

•I

OL = 48mA (commercial) and 32mA (military)

• Clamp diodes on all inputs for ringing suppression

• CMOS power levels (1mW typ. static)

• TTL input and output level compatible

• CMOS output level compatible

• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT54/74FCT800 series is built using an advanced

dual metal CMOS technology.

The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular ‘373 function.

All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-imped­ance state.

PRE

CLR

LE

OE

D0

D
LE

CLR

DN

P

Q

0

Y

D
LE

CLR

P

Q

N

Y

2607 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1994

1994 Integrated Device Technology, Inc. 7.22 DSC-4603/2

1

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

1

OE

2

D

0

3

D1

4

D2
D3
D4
D5
D6
D7
D

D9

GND

8

P24-1
D24-1

5

E24-1

6
7

SO24-2

8
9
10

11
12

&

DIP/CERPACK/SOIC

TOP VIEW

24

VCC

23

Y

0

22

Y1

21

Y2

20

Y3

19

Y4

18

5

Y

17

Y6

16

Y7
Y8

15
14

Y9

13

LE

INDEX

D2
D3
D4

NC

D
D6
D7

1

D

D0

32

4
5
6
7
8
9

5

10
11

12 13

D8

D9

OE

NC

1

L28-1

NC

GND

CC

V

LE

Y0

Y1

262728

25

Y2

24

Y3

23

Y4

22

NC
Y

5

21
20

Y6

19

1817161514

9

Y

Y7

Y8

LCC

TOP VIEW

2607 drw 02

2607 drw 03

PIN DESCRIPTION

Name I/O Description

CLR

DI I The latch data inputs.
LE I The latch enable input. The latches are

YI O The 3-state latch outputs.

OE

PRE

I When

CLR

is LOW, the outputs are

LOW if OE is LOW. When

CLR

is HIGH,

data can be entered into the latch.

transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.

I The output enable control. When OE is

LOW, the outputs are enabled. When

OE

is HIGH, the outputs (Y

I) are in the

high-impedance (off) state.

I Preset line. When

PRE

is LOW, the
outputs are HIGH if OE is LOW. Preset
overrides

CLR

.

2607 tbl 01

LE D

(1)

Inter-

I

nal

Q

Out-

puts

I

Y

I

Function

FUNCTION TABLE

Inputs

CLR

PRE

CLR

PREOEOE

H H H X X X Z High Z
H H H H L L Z High Z
H H H H H H Z High Z
H H H L X NC Z Latched (High Z)
H H L H L L L Transparent
H H L H H H H Transparent
H H L L X NC NC Latched
H L L X X H H Preset

L H L X X L L Clear
L L L X X H H Preset
L H H L X L Z Latched (High Z)

H L H L X H Z Latched (High Z)

NOTE: 2607 tbl 02

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance

7.22 2

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

Terminal Voltage

–0.5 to VCC –0.5 to VCC V
with Respect to
GND

TA Operating

0 to +70 –55 to +125 °C

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C

Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C

Temperature

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

120 120 mA

Current

NOTE: 2607 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V

2. Input and V

3. Outputs and I/O terminals only.

CC by +0.5V unless otherwise noted.

CC terminals only.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

C

IN

Input
Capacitance

C

OUT

Output
Capacitance

NOTE: 2607 tbl 04

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

V

OUT

= 0V 8 12 pF

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA

VI = 2.7V — — 5

II L Input LOW Current VI = 0.5V — — –5

VI = GND — — –5

IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA

Output Current VO = 2.7V — — 10

IOZL VO = 0.5V — — –10

VO = GND — — –10
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.

(3)

, VO = GND –75 –120 — mA

VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

VCC = Min. IOH = –300µAVHC VCC —
VIN = VIH or VIL IOH = –15mA MIL. 2.4 4.3 —

IOH = –24mA COM'L. 2.4 4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

VCC = Min. IOL = 300µA — GND VLC
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5

IOL = 48mA COM'L. — 0.3 0.5

NOTES: 2607 tbl 05

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

CC = 5.0V, +25°C ambient and maximum loading.

(2)

Max. Unit

(4)

(4)

(4)

(4)

(4)

7.22 3

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol Parameter Test Conditions

ICC

∆ICC
ICCD Dynamic Power Supply

Quiescent Power Supply Current VCC = Max.

IN ≥ VHC; V IN ≤ VLC

V
Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.

IN = 3.4V

V

VCC = Max.

(4)

Current

Outputs Open

OE

= GND

CC

LE = V

(3)

(1)

V

IN ≥ VHC
IN ≤ VLC

V

Min. Typ.

— 0.2 1.5 mA

— 0.5 2.0 mA
— 0.15 0.25 mA/

One Input Toggling

50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.

Outputs Open

fi = 10MHz

VIN ≥ VHC
V

IN ≤ VLC

(FCT)

— 1.7 4.0 mA

50% Duty Cycle

OE

= GND

LE = V

CC

V

IN = 3.4V
IN = GND

V

— 2.0 5.0

One Bit Toggling

VCC = Max.

Outputs Open

fi = 2.5MHz

VIN ≥ VHC

IN ≤ VLC

V
(FCT)

— 3.2 6.5

50% Duty Cycle

OE

= GND

LE = V

CC

V

IN = 3.4V
IN = GND

V

— 5.2 14.5

Eight Bits Toggling

NOTES: 2607 tbl 06

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VC

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I
D

H = Duty Cycle for TTL Inputs High
T = Number of TTL Inputs at DH

N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f
f

i = Input Frequency

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

C = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

7.22 4

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT841A FCT841B FCT841C

Com'l. Mil. Com'l. Mil. Com'l. Mil.

(2)

(1)

Min.

Symbol Parameter Conditions

tPLH
tPHL

Propagation Delay
D

I to YI (LE = HIGH)

CL = 50pF

R

L = 500Ω

CL = 300pF

RL = 500Ω
tPLH
tPHL

Propagation Delay
LE to Y

I

CL = 50pF

R

L = 500Ω

CL = 300pF

RL = 500Ω
tPLH Propagation Delay,

PRE

to YI CL = 50pF 1.5 12.0 1.5 14.0 1.5 8.0 1.5 10.0 1.5 7.0 1.5 9.0 ns

(4)

(4)

Max. Min.

1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns

1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0

1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns

1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0

tPHL RL = 500Ω 1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 9.0 1.5 12.0
tPHL Propagation Delay,

CLR

to YI 1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 9.0 1.5 10.0 ns

tPLH 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5 9.0 1.5 9.0
tPZH

tPZL

Output Enable Time OE to YI CL = 50pF

R

L = 500Ω

CL = 300pF

1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 ns

(4)

1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0

RL = 500Ω

L = 500Ω

(4)

1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 ns

1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3

tPHZ
tPLZ

Output Disable Time OE to Y I CL = 5pF

RL = 500Ω

CL = 50pF

R
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns

tH Data to LE Hold Time RL = 500Ω 2.5 — 3.0 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tW LE Pulse Width
tW
tW

PRE

Pulse Width

CLR

Pulse Width

tREM Recovery Time
tREM Recovery Time

NOTES: 2607 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. These parameters are guaranteed but not tested.

4. These conditions are guaranteed but not tested.

(3)

PRE
CLR

HIGH 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns

(3)

LOW 5.0 — 7.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns

(3)

LOW 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
to LE 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
to LE 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max.

Unit

7.22 5

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

7.0V

SWITCH POSITION

Test Switch

Open Drain

Pulse

Generator

500Ω

V

V

IN

OUT

D.U.T.

50pF

T

R

CL

500Ω

DEFINITIONS: 2607 tbl 08

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Disable Low Closed

Enable Low

All Other Tests Open

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tSU

tH

tREM

tH

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V

0V

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

1.5V

tW

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

tPLH

tPHL

tPLH tPHL

3V

1.5V
0V

V

OH

1.5V

VOL

3V

1.5V
0V

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

PLZtPZL

t

OUTPUT

NORMALLY

LOW

SWITCH
CLOSED

3.5V

1.5V

tPZH tPHZ

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

SWITCH
OPEN

1.5V
0V

F ≤ 2.5ns; tR ≤ 2.5ns

0.3V

0.3V

1.5V
0V

3.5V

VOL

VOH

0V

2607 drw 04

7.22 6

IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT XX

Temp. Range

FCT

XXXX

Device TypeXPackage

X

Process

Blank
B

P
D
E
L
SO

841A
841B
841C

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

10-Bit Non-Inverting Latch

–55°C to +125°C
0°C to +70°C

2607 drw 05

7.22 7