Datasheet IDT54FCT821AT, IDT54FCT821BT, IDT54FCT821CT, IDT54FCT823AT, IDT54FCT823BT Datasheet (IDT)

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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS

Integrated Device Technology, Inc.

IDT54/74FCT821AT/BT/CT

IDT54/74FCT823AT/BT/CT/DT

IDT54/74FCT825AT/BT/CT

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility

– VOH = 3.3V (typ.)
– V

OL = 0.3V (typ.)

– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation

Enhanced versions

– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for FCT821T/FCT823T/FCT825T:

– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis­ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (EN) and Clear (

interfacing in high-performance microprogrammed systems.
The FCT825T are 8-bit buffered registers with all the FCT823T
controls plus multiple enables (OE1, OE2, OE3) to allow multi­user control of the interface, e.g., CS, DMA and RD/WR. They
are ideal for use as an output port requiring high I

The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.

CLR

) – ideal for parity bus

OL/IOH.

D

EN

CLR

CP

OE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

0

CL

D

Q

CP

Q

Y

0

D

N

CL

D

Q

CP

Q

Y

N

2567 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc 6.21 DSC-4202/5

6.21 1
1

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

FCT821 10-BIT REGISTER

OE

D

0

2

D1

3
4
5

SO24-2

6

SO24-7

7

SO24-8

8
9
10

11
12

P24-1

D24-1

&

E24-1

D2
D3
D4
D5
D6
D7
D

D9

GND

8

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

FCT823 9-BIT REGISTER

1

OE

2

0

D

3

D

1

D

2

D

3

D

4

D

5

D

6

D

7
8

D

CLR

GND

DIP/SOIC/SSOP/QSOP/CERPACK

P24-1

4

D24-1

5

SO24-2

6

SO24-7

7

SO24-8

8

&

9

E24-1

10
11

12

TOP VIEW

24
23
22
21
20
19
18
17
16
15
14
13

24
23
22
21
20
19
18
17
16
15
14
13

VCC1
Y
Y1
Y2
Y3
Y4
Y
Y6
Y7
Y8

Y9
CP

V
Y
Y
Y
Y
Y
Y
Y
Y
Y

EN
CP

0

5

CC
0
1
2
3
4
5
6
7
8

INDEX

INDEX

D2
D3
D4

NC

D
D6
D7

D
D

D

NC

D
D

D

1

D0

D

32

4
5
6
7
8
9

5

10
11

1213

D9

D8

NC

OE

1

L28-1

NC

GND

CC

V

CP

Y0

Y1

262728

Y2

25

Y3

24

Y4

23

NC

22

Y

21
20
19

5

Y6
Y7

1817161514

9

Y8

Y

2567 drw 02

LCC

TOP VIEW

0

1

D

D

4

2
3

4

32
5
6
7
8
9

5
6

10
11

7

1213

8

D

CLR

NC

OE

1

L28-1

NC

GND

CC

V

CP

0

Y

1817161514

EN

1

Y

262728

25

Y

2

24

Y

3

23

Y

4

NC

22
21
20
19

8

Y

5

Y
Y

6

Y

7

2567 drw 03

LCC

TOP VIEW

FCT825 8-BIT REGISTER

OE1
OE2

CLR
GND

2

D0

3

D1

4

P24-1
5
6
7
8
9
10

D24-1

SO24-2
SO24-8

&

E24-1

D2
D3
D4
D5
D6
D7

11
12

DIP/SOIC/QSOP/CERPACK

TOP VIEW

24
23
22
21
20
19
18
17
16

15
14
13

VCC1
OE3

0

Y
Y1
Y2
Y3
Y4

5

Y
Y6
Y7
EN
CP

INDEX

D1
D
D3

NC

D
D5
D6

2

1

0

D

OE

OE

32

4
5
6

2

7
8
9

4

L28-1

10
11

1213

7

D

GND

CLR

1

NC

NC

3

VCCOE

CP

EN

0

Y

262728

Y1

25

Y2

24

Y3

23

NC

22

Y

21
20
19

4

Y5
Y6

1817161514

7

Y

2567 drw 04

LCC

TOP VIEW

6.21 2

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Names I/O Description

DI I The D flip-flop data inputs.

CLR

CP I Clock Pulse for the Register; enters

YI O The register 3-state outputs.

EN

OE

I When the clear input is LOW and OE is

LOW, the Q

I outputs are LOW. When

the clear input is HIGH, data can be
entered into the register.

data into the register on the LOW-to­HIGH transition.

I Clock Enable. When the clock enable is

LOW, data on the D
to the Q

I output on the LOW-to-HIGH

I input is transferred

clock transition. When the clock enable
is HIGH, the Q

I outputs do not change

state, regardless of the data or clock
input transitions.

I Output Control. When the OE input is

HIGH, the Y

I outputs are in the high-

impedance state. When the OE input is
LOW, the TRUE register data is present
at the Y

I outputs.

2567 tbl 01

FUNCTION TABLE

Inputs

OEOECLR

CLRENEN

H

H

H

H

H

L

H

H

L

H

H

H

H

H

L

H

L

H

NOTE: 2567 tbl 02

1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance

L
L

L

X

L

X
H
H

L
L
L
L

(1)

Internal/
Outputs

DI CP QI YI

L

↑

L

H
X

X
X
X

L

H

L

H

↑

X
X
X
X

↑
↑
↑
↑

H

L

L
NC
NCZNC

L

H

L

H

Z
Z

Z
L

Z
Z
L

H

Function

High Z

Clear

Hold

Load

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

TA Operating

Terminal Voltage
with Respect to
GND

–0.5 to

CC +0.5

V

–0.5 to

VCC +0.5

0 to +70 –55 to +125 °C

V

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C
Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C
Temperature

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

–60 to +120 –60 to +120 mA
Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed

CC by +0.5V unless otherwise noted.

V

2. Input and V

3. Outputs and I/O terminals only.

CC terminals only.

2567 lnk 03

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

COUT Output

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

2567 lnk 04

6.21 3

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

V

IH

V

IL

I

I H

I

I L

I

OZH

I

OZL

II Input HIGH Current
V

IK

V

H

I

CC

Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
Input HIGH Current
Input LOW Current

(4)

(4)

VI = 0.5V — —

VCC = Max. VI = 2.7V — —

High Impedance Output Current VCC = Max. VO = 2.7V — —

(4)

(4)

VCC = Max., VI = V

—

CC

(Max.) — —

IN

= –18mA — –0.7 –1.2 V

VO = 0.5V — —

CC

(3-State Output pins)

Clamp Diode Voltage VCC = Min., I
Input Hysteresis
Quiescent Power Supply Current VCC = Max., VIN = GND or V

(1)

Min. Typ.

— 200 — mV
— 0.01 1 mA

(2)

Max. Unit

±
±
±
±
±

1
1
1
1
1

µ

A

µ

A

µ

A

2567 lnk 05

OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T

Symbol Parameter Test Conditions

VOH Output HIGH Voltage VCC = Min.

IN = VIH or VIL

V

VOL Output LOW Voltage VCC = Min.

IN = VIH or VIL

V

IOS Short Circuit Current VCC = Max., VO = GND
IOFF Input/Output Power Off Leakage

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test limit for this parameter is ±5µA at T

5. This parameter is guaranteed but not tested.

(5)

A = –55°C.

VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

(3)

(1)

IOH = –6mA MIL.

OH = –8mA COM'L.

I
IOH = –12mA MIL.

OH = –15mA COM'L.

I
IOL = 32mA MIL.

OL = 48mA COM'L.

I

Min. Typ.

2.4 3.3 — V

2.0 3.0 — V

— 0.3 0.5 V

–60 –120 –225 mA

(2)

Max. Unit

2567 lnk 06

6.21 4

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC

Quiescent Power Supply Current
TTL Inputs HIGH

ICCD Dynamic Power Supply Current

(4)

VCC = Max.
V

IN = 3.4V

VCC = Max.

(3)

Outputs Open

OE

= EN = GND

(1)

V

IN = VCC

V

IN = GND

Min. Typ.

— 0.5 2.0 mA
— 0.15 0.25 mA/

One Input Toggling
50% Duty Cycle

IC Total Power Supply Current

(6)

VCC = Max.
Outputs Open
f

CP= 10MHz

IN = VCC

V
V

IN = GND

— 1.5 3.5 mA

50% Duty Cycle

OE

= EN = GND

One Bit Toggling

VIN = 3.4V
V

IN = GND

— 2.0 5.5

at fi = 5MHz
50% Duty Cycle
VCC = Max.
Outputs Open
f

CP= 10MHz

IN = VCC

V
V

IN = GND

— 3.8 7.3

50% Duty Cycle

OE

= EN = GND

Eight Bits Toggling

VIN = 3.4V
V

IN = GND

— 6.0 16.3

at fi = 2.5MHz
50% Duty Cycle

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I

CC = Quiescent Current

∆I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

D

H = Duty Cycle for TTL Inputs High

N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

N

i = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V). All other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

(5)

(5)

2567 tbl 07

6.21 5

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT821/823/825AT FCT821/823/825BT

Com'l. Mil. Com'l. Mil.

= 500

= 500

= 500

(1)

Ω

(4)

Ω

Ω

Ω

(4)

Ω

(4)

Ω

Symbol Parameter Condition

t

PLH

t

PHL

Propagation Delay

I

CP to Y

(OE = LOW)

CL = 50pF

R

L

CL = 300pF

RL = 500

t

SU

t

H

t

SU

t

H

t

PHL

t

REM

t

W

t

W

t

PZH

t

PZL

Set-up Time HIGH or LOW

I

to CP

D
Hold Time HIGH or LOW

I

to CP

D
Set-up Time HIGH or LOW

EN

to CP

Hold Time HIGH or LOW

EN

to CP

Propagation Delay,

Recovery Time

Clock Pulse Width
HIGH or LOW

CLR

Pulse Width LOW

Output Enable Time OE to Y

CLR

CLR

to Y

to CP

CL = 50pF

R

L

I

I

CL = 50pF

R

L

CL = 300pF

RL = 500

t

PHZ

t

PLZ

Output Disable Time

OE

to Y

I

CL = 5pF

RL = 500

CL = 50pF

R

L

= 500

Ω

NOTES: 2567 tbl 08

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

4. This condition is guaranteed but not tested.

Min

(2)

.

Max. Min

(2)

.

Max. Min

(2)

.

Max. Min

(2)

.

Max. Unit

1.5 10.0 1.5 11.5 1.5 7.5 1.5 8.5 ns

1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0

4.0 — 4.0 — 3.0 — 3.0 — ns

2.0 — 2.0 — 1.5 — 1.5 — ns

4.0 — 4.0 — 3.0 — 3.0 — ns

2.0 — 2.0 — 0 — 0 — ns

1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns

6.0 — 7.0 — 6.0 — 6.0 — ns

7.0 — 7.0 — 6.0 — 6.0 — ns

6.0 — 7.0 — 6.0 — 6.0 — ns

1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns

1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0

1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 ns

1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0

6.21 6

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT821/823/825CT FCT823DT

Com'l. Mil. Com'l.

= 500

= 500

= 500

(1)

Ω

(4)

Ω

Ω

Ω

(4)

Ω

(4)

Ω

Symbol Parameter Condition

t

PLH

t

PHL

Propagation Delay

I

CP to Y

(OE = LOW)

CL = 50pF

R

L

CL = 300pF

RL = 500

t

SU

t

H

t

SU

t

H

t

PHL

t

REM

t

W

t

W

t

PZH

t

PZL

Set-up Time HIGH or LOW

I

to CP

D
Hold Time HIGH or LOW

I

to CP

D
Set-up Time HIGH or LOW

EN

to CP

Hold Time HIGH or LOW

EN

to CP

Propagation Delay,

Recovery Time

Clock Pulse Width
HIGH or LOW

CLR

Pulse Width LOW

Output Enable Time OE to Y

(3)

CLR

CLR

to CP

(3)

to Y

CL = 50pF

R

L

I

I

CL = 50pF

R

L

CL = 300pF

RL = 500

t

PHZ

t

PLZ

Output Disable Time

OE

to Y

I

CL = 5pF

RL = 500

CL = 50pF

R

L

= 500

Ω

NOTES: 2567 tbl 09

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. This parameter is guaranteed but not tested.

4. This condition is guaranteed but not tested.

Min

(2)

.

Max. Min

(2)

.

Max. Min

(2)

.

Max. Unit

1.5 6.0 1.5 7.0 1.5 5.0 ns

1.5 12.5 1.5 13.5 1.5 8.5

3.0 — 3.0 — 2.0 — ns

1.5 — 1.5 — 1.0 — ns

3.0 — 3.0 — 3.0 — ns

0—0— 0 — ns

1.5 8.0 1.5 8.5 1.5 5.0 ns

6.0 — 6.0 — 3.0 — ns

6.0 — 6.0 — 3.0 — ns

6.0 — 6.0 — 3.0 — ns

1.5 7.0 1.5 8.0 1.5 4.8 ns

1.5 12.5 1.5 13.5 1.5 9.0

1.5 6.0 1.5 6.0 1.5 4.0 ns

1.5 6.5 1.5 6.5 1.5 4.0

6.21 7

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

V

CC

V

OUT

Pulse

Generator

V

IN

D.U.T.

50pF

T

R

C

L

SET-UP, HOLD AND RELEASE TIMES

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

t

SU

t

SU

t

REM

t

H

t

H

500

500

Ω

Ω

2567 drw 05

2567 drw 06

7.0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

SWITCH POSITION

Test Switch

Open Drain
Disable Low

Closed

Enable Low

All Other Tests

DEFINITIONS:

L= Load capacitance: includes jig and probe capacitance.

C

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

Open

PULSE WIDTH

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

t

W

2567 lnk 10

1.5V

1.5V

2567 drw 07

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

t

PLH

OUTPUT

t

OPPOSITE PHASE

INPUT TRANSITION

PLH

t

t

PHL

PHL

3V

1.5V
0V

OH

V

1.5V

V

OL

3V

1.5V
0V

2567 drw 08

ENABLE AND DISABLE TIMES

ENABLE DISABLE

3V

CONTROL

INPUT

t

t

PHZ

PLZ

F ≤ 2.5ns; tR ≤ 2.5ns

t

PZL

OUTPUT

NORMALLY

OUTPUT

NORMALLY

HIGH

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable­HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t

LOW

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

0.3V

0.3V

1.5V
0V

3.5V

V

OL

V

OH

0V

2567 drw 09

6.21 8

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

Temp. Range

XX

XXXX

Device TypeXPackage

X

Process

Blank
B

P
D
E
L
SO
PY
Q

821AT
823AT
825AT
821BT
823BT
825BT
821CT
823CT
825CT
823DT

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package

10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
8-Bit Non-Inverting Register

–55°C to +125°C
0°C to +70°C

2567 drw 10

6.21 9