Datasheet IDT74FCT807CTSOB, IDT74FCT807CTSO, IDT74FCT807CTQB, IDT74FCT807CTQ, IDT74FCT807CTPYB Datasheet (Integrated Device Technology)
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Integrated Device Technology, Inc.
FAST CMOS
1-TO-10
CLOCK DRIVER
IDT54/74FCT807BT/CT
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 250ps (max.)
• Very low duty cycle distortion < 350ps (max.)
• High speed: propagation delay < 2.5ns (max.)
• 100MHz operation
• TTL compatible inputs and outputs
• TTL level output voltage swings
• 1:10 fanout
• Output rise and fall time < 1.5ns (max.)
• Low input capacitance: 4.5pF typical
• High Drive: -32mA I
OH, 48mA IOL
• ESD > 2000V per MIL STD-883, Method 3015;
FUNCTIONAL BLOCK DIAGRAM
IN
O1
O2
O3
O4
O5
O6
O7
O8
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT807BT/CT clock driver is built using
advanced dual metal CMOS technology. This low skew clock
driver features 1:10 fanout, providing minimal loading on the
preceding drivers. The IDT54/74FCT807BT/CT offers low
capacitance inputs with hysteresis for improved noise margins.
TTL level outputs and multiple power and grounds reduce
noise. The device also features -32/48mA drive capability for
driving low impedance traces.
PIN CONFIGURATIONS
IN
GND
O
VCC
O
1
2
1
2
3
4
5
P20-1
D20-1
SO20-2
SO20-7
6
GND
O
VCC
O
GND
3
4
SO20-8
&
7
E20-1
8
9
10 11
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
20
19
18
17
16
15
14
13
12
V
CC
O
10
O
9
GND
O
8
CC
V
O
7
GND
O
6
O
5
3017 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
O9
O10
3017 drw 01
INDEX
CC
V
O
GND
O3
V
CC
2
1
GND
O
3 2 20 19
4
5
6
7
8
910111213
O4
IN
1
L20-2
5
O
GND
LCC
TOP VIEW
CC
V
O6
O10
18
17
16
15
14
GND
O9
GND
O8
CC
V
O7
3017 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995
1995 Integrated Device Technology, Inc. 9.3 DSC-4242/3
1
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
IN Input
Ox Outputs
3017 tbl 01
CC
(1)
–0.5 to V
+0.5
CC
3017 lnk 03
V
CC by
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Commercial Military Unit
(2)
VTERM
VTERM
TA Operating
TBIAS Temperature
TSTG Storage
IOUT DC Output
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability. No terminal voltage may exceed V
+0.5V unless otherwise noted.
2. Input and V
3. Output and I/O terminals.
Terminal Voltage
with Respect to
GND
(3)
Terminal Voltage
with Respect to
GND
Temperature
Under Bias
Temperature
Current
CC terminals.
–0.5 to +7.0 –0.5 to +7.0 V
–0.5 to V
+0.5
0 to +70 –55 to +125 °C
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
–60 to +120 –60 to +120 mA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
Capacitance
COUT Output
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 4.5 6.0 pF
VOUT = 0V 5.5 8.0 pF
3017 lnk 02
9.3 2
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
(1)
Min. Typ.
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
(5)
(5)
VCC = Max. VI = 2.7V — — ±1 µA
VCC = Max. VI = 0.5V — — ±1 µA
II H Input HIGH Current
II L Input LOW Current
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
(5)
(5)
VO = 0.5V — — ±1 µA
VCC = Max., VI = VCC (Max.) — — ±1 µA
IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN= –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
VOH Output HIGH Voltage VCC = Min.
IN = VIH or VIL
V
VOL Output LOW Voltage VCC = Min.
IN = VIH or VIL
V
IOFF Input/Output Power Off Leakage
VH Input Hysteresis for all inputs — — 150 — mV
ICCL
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
(5)
VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
(3)
, VO = GND –60 –120 –225 mA
IOH = –12mA MIL.
OH = –15mA COM'L.
I
IOH = –24mA MIL.
OH = –32mA COM'L.
I
IOL = 32mA MIL.
OL = 48mA COM'L.
I
2.4 3.3 — V
2.0 3.0 —
(4)
— 0.3 0.55 V
ICCH
ICCZ
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at T
A = –55°C.
(2)
Max. Unit
3017 lnk 04
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
ICCD Dynamic Power Supply Current
(3)
VCC = Max.
V
IN = 3.4V
VCC = Max.
Input toggling
(1)
VIN = VCC
V
IN = GND
Min. Typ.
— 0.5 2.0 mA
— 0.4 0.6 mA/
50% Duty Cycle
Outputs Open
IC Total Power Supply Current
(5)
VCC = Max.
Input toggling
VIN = VCC
V
IN = GND
— 20.0 30.5
50% Duty Cycle
Outputs Open
fi = 50MHz
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input; (V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
C = IQUIESCENT + IINPUTS + IDYNAMIC
6. I
IC = ICC + ∆ICC DHNT + ICCD (fi)
CC = Quiescent Current (ICCL, ICCH and ICCZ)
I
∆I
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
H = Duty Cycle for TTL Inputs High
D
T = Number of TTL Inputs at DH
N
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
i= Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
CC = 5.0V, +25°C ambient.
IN = 3.4V); all other inputs at VCC or GND.
CC formula. These limits are guaranteed but not tested.
VIN = 3.4V
V
IN = GND
— 20.3 31.3
(2)
Max. Unit
(4)
(4)
MHz
mA
3017 tbl 05
9.3 3
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
IDT54/74FCT807BT IDT54/74FCT807CT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions
tPLH
tPHL
Propagation Delay 50Ω to VCC/2,
L = 10pF
C
(2)
Min.
Max. Min.
1.3 2.7 1.3 2.5 ns
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
(1)
tR Output Rise Time (See figure 1) — 1.5 — — 1.5 — ns
tF Output Fall Time or 50Ω ac — 1.5 — — 1.5 — ns
tSK(o) Output skew: skew between outputs of
same package (same transition)
tSK(p) Pulse skew: skew between opposite
transitions of same output (|t
PHL -– tPLH|)
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
termination,
L = 10pF
C
(See figure 2)
f ≤ 100MHz
Outputs
connected in
groups of two
— 0.5 — — 0.25 — ns
— 0.5 — — 0.35 — ns
— 0.9 — — 0.65 — ns
speed grade
3017 tbl 06
IDT54/74FCT807BT IDT54/74FCT807CT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions
tPLH
tPHL
Propagation Delay CL = 30pF
f ≤ 67MHz
(2)
Min.
Max. Min.
1.5 3.8 1.5 3.5 ns
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
(1)
tR Output Rise Time (See figure 3) — 1.5 — — 1.5 — ns
tF Output Fall Time — 1.5 — — 1.5 — ns
tSK(o) Output skew: skew between outputs of
— 0.5 — — 0.25 — ns
same package (same transition)
tSK(p) Pulse skew: skew between opposite
transitions of same output (|t
PHL -– tPLH|)
tSK(t) Package skew: skew between outputs of
— 0.5 — — 0.35 — ns
— 0.9 — — 0.75 — ns
different packages at same power supply
voltage, temperature, package type and
speed grade
3017 tbl 07
IDT54/74FCT807BT IDT54/74FCT807CT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions
tPLH
tPHL
Propagation Delay CL = 50pF
f ≤ 40MHz
(2)
Min.
Max. Min.
1.5 3.8 1.5 3.5 ns
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
(1)
tR Output Rise Time (See figure 4) — 1.5 — — 1.5 — ns
tF Output Fall Time — 1.5 — — 1.5 — ns
tSK(o) Output skew: skew between outputs of
— 0.5 — — 0.35 — ns
same package (same transition)
tSK(p) Pulse skew: skew between opposite
transitions of same output (|t
PHL -– tPLH|)
tSK(t) Package skew: skew between outputs of
— 0.60 — — 0.45 — ns
— 1.0 — — 0.75 — ns
different packages at same power supply
voltage, temperature, package type and
speed grade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
limits do not imply skew.
CC, operating temperature and process parameters. These propagation delay
3017 tbl 08
Unit
Unit
Unit
9.3 4
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS
50Ω TO V
Pulse
Generator
Pulse
Generator
CC/2, CL = 10pF
V
CC
V
IN
D.U.T.
T
R
V
V
IN
D.U.T.
R
T
CC
V
OUT
V
OUT
100
V
Ω
30pF
C
L
CC
100
3017 drw 04
50Ω AC TERMINATION, CL = 10pF
V
CC
Ω
V
Pulse
Generator
IN
D.U.T.
10pF
R
T
The capacitor value for ac termination is determined by the operating
frequency. For very low frequencies a higher capacitor value should be
selected.
C
L = 50pF CIRCUITCL = 30pF CIRCUIT
Figure 2.Figure 1.
V
IN
Pulse
Generator
R
T
V
CC
D.U.T.
V
OUT
220pF
V
OUT
50
Ω
C
10pF
3017 drw 05
50pF
L
3017 drw 06
Figure 4.Figure 3.
ENABLE AND DISABLE TIME CIRCUIT ENABLE AND DISABLE TIME
SWITCH POSITION
V
Pulse
Generator
CC
500
V
V
IN
OUT
7.0V
Ω
D.U.T.
DEFINITIONS:
C
L= Load capacitance: includes jig and probe capacitance.
T = Termination resistance: should be equal to ZOUT of the Pulse
R
Generator.
R
T
Figure 5.
50pF
C
L
500
Ω
3017 drw 08
Test Switch
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
3017 drw 07
Closed
Open
3017 lnk 09
9.3 5
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST WAVEFORMS
PACKAGE DELAY
INPUT
OUTPUT
PULSE SKEW - t
INPUT
OUTPUT
SK(p) PACKAGE SKEW - tSK(t)
tPLH
tPLH tPHL
tR
tPHL
tSK(p) = |tPHL - tPLH|
OUTPUT SKEW- t
3V
1.5V
0V
VOH
2.0V
1.5V
0.8V
VOL
tF
INPUT
OUTPUT 1
OUTPUT 2
SK(o)
tPLH1
tPLH2
tSK(o)
tPHL1
tPHL2
tSK(o)
3V
1.5V
0V
OH
V
1.5V
V
OL
VOH
1.5V
OL
V
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
3V
1.5V
0V
OH
V
1.5V
OL
V
3017 drw 09
INPUT
PACKAGE 1 OUTPUT
tPLH1
t
SK(t)
tPHL1
tSK(t)
3017 drw 10
3V
1.5V
0V
OH
V
1.5V
OL
V
VOH
1.5V
V
PACKAGE 2 OUTPUT
tPLH2
tPHL2
OL
ENABLE AND DISABLE TIMES
ENABLE DISABLE
3V
CONTROL
INPUT
t
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; t
SWITCH
OPEN
1.5V
0V
PLZt PZL
t
PHZ
F ≤ 2.5ns; tR ≤ 2.5ns
0.3V
0.3V
1.5V
0V
3.5V
V
OL
V
OH
0V
3017 drw 13
3017 drw 11
SK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
t
Package 1 and Package 2 are same device type and speed grade
3017 drw 12
9.3 6
IDT54/74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX
Temp. Range
FCT
XXXX
Device Type
X
Package
X
Process
Blank
B
P
D
SO
L
E
PY
Q
807BT
807CT
54
74
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Shrink Small Outline IC
Quarter-size Small Outline IC
1-to-10 Clock Driver
–55
°
C to +125°C
0
°
C to +70°C
3017 drw 14
9.3 7
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