Datasheet IDT74FCT543DB, IDT74FCT543D, IDT74FCT543CPB, IDT74FCT543CP, IDT74FCT543CLB Datasheet (Integrated Device Technology)



Integrated Device Technology, Inc.

FAST CMOS
OCTAL LATCHED
TRANSCEIVER

IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C

FEATURES:

• IDT54/74FCT543 equivalent to FAST speed

• IDT54/74FCT543A 25% faster than FAST

• IDT54/74FCT543C 40% faster than FAST

• Equivalent to FAST output drive over full temperature
and voltage supply extremes

•IOL = 64mA (commercial), 48mA (military)

• Separate controls for data flow in each direction

• Back-to-back latches for storage

• CMOS power levels (1mW typ. static)

• Substantially lower input current levels than FAST
(5µA max.)

• TTL input and output level compatible

• CMOS output level compatible

• Product available in Radiation Tolerant and Radiation
Enhanced versions

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAMS

Q

D

LE

DESCRIPTION:

The IDT54/74FCT543/A/C is a non-inverting octal trans­ceiver built using an advanced dual metal CMOS technology.
These devices contain two sets of eight D-type latches with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (

be LOW in order to enter data from A0–A7 or to take data from
B0–B7, as indicated in the Function Table. With
a LOW signal on the A-to-B Latch Enable (
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the

LEAB

signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With

CEAB

and

OEAB

both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the

CEBA, LEBA

and

DETAIL A

OEBA

inputs.

B0

CEAB

LEAB

) input must

CEAB

LOW,

) input makes

D

A0

A1
A2
A3
A4
A5
A6
A7

OEBA

CEBA

LEBA

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.

DETAIL A x 7

Q

LE

B1
B2
B3
B4
B5

B6
B7

OEAB

CEAB

LEAB

2614 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992

1992 Integrated Device Technology, Inc. 7.17 DSC-4602/3

1

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT54/74FCT861 10-BIT TRANSCEIVERS

LEBA

OEBA

A
A1
A2
A3
A4
A5
A
A7

CEAB

GND

1
2
3

0

P24-1,

4

D24-1,

5

SO24-2

6
7

E24-1

8
9

6

10
11
12

DIP/SOIC/CERPACK

TOP VIEW

24

Vcc

23

CEBA

22
21
20
19

&

18
17
16
15
14
13

0

B
B1
B2
B3
B4
B5
B6
B7

LEAB
OEAB

PIN DESCRIPTION

Pin Names Description

OEAB
OEBA
CEAB
CEBA
LEAB
LEBA

0–A7 A-to-B Data Inputs or B-to-A 3-State Outputs

A

0–B7 B-to-A Data Inputs or A-to-B 3-State Outputs

B

A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)

LOGIC SYMBOL

2614 tbl 02

INDEX

A1
A2
A3

NC

A4
A5
A6

A0LEBA

OEBA

NC

Vcc

432128 27 26

5
6
7
8
9
10
11

L28-1

12 13 14 15 16 17 18

A7

GND

CEAB

NC

CEBA

LEAB

OEAB

B0

25
24
23
22
21
20
19

7

B

1

B
B2
B3
NC
B4
B5
B6

2614 drw 02

LCC

TOP VIEW

FUNCTION TABLE

(1,2)

For A-to-B (Symmetric with B-to-A)

Latch Output

Inputs Status Buffers

CEAB

CEAB

— H — Storing —
— — H — High Z

NOTES: 2614 tbl 01

1. * Before

H = HIGH Voltage Level
L = LOW Voltage Level
— = Don’t Care or Irrelevant

2. A-to-B data flow shown; B-to-A flow control is the same, except using

CEBA, LEBA

LEAB

LEAB

OEAB

OEAB

A-to-B B

0–B7

H — — Storing High Z

L L L Transparent Current A Inputs
L H L Storing Previous* A Inputs

LEAB

LOW-to-HIGH Transition

and

OEBA

.

LEAB CEAB CEBA LEBA
A

0

A1
A2
A3
A4
A5
A6
A7
OEBA

B0
B1
B2
B3
B4
B5
B6
B7

OEAB

2614 drw 03

7.17 2

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

V

TERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND

(3)

V

TERM

Terminal Voltage –0.5 to VCC –0.5 to VCC V
with Respect
to GND

T

A Operating 0 to +70 –55 to +125 °C

Temperature

T

BIAS Temperature –55 to +125 –65 to +135 °C

Under Bias

T

STG Storage –55 to +125 –65 to +150 °C

Temperature

P

T Power Dissipation 0.5 0.5 W

I

OUT DC Output Current 120 120 mA

NOTES: 2614 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V

2. Inputs and V

3. Outputs and I/O terminals only.

CC by +0.5V unless otherwise noted.

CC terminals only.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

IN Input Capacitance VIN = 0V 6 10 pF

C

I/O I/O Capacitance VOUT = 0V 8 12 pF

C

NOTE: 2614 tbl 04

1. This parameter is guaranteed by characterization data and not tested.

(1)

Conditions Typ. Max. Unit

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

IH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

V

IL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

V

IH Input HIGH Current VCC = Max. VI = VCC ——5µA

I

(Except I/O pins) V

(1)

I = 2.7V — — 5

Min. Typ.

IIL Input LOW Current VI = 0.5V ——–5

(Except I/O pins) V

IH Input HIGH Current VCC = Max. VI = VCC ——15µA

I

(I/O pins Only) V

I = GND — — –5

I = 2.7V — — 15

IIL Input LOW Current VI = 0.5V — — –15

(I/O pins Only) V

IK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V

V

OS Short Circuit Current V CC = Max.

I

OH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V

V

CC = Min. IOH = –300µAVHC

V

IN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —

V

OL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V

V

CC = Min. IOL = 300µA — GND VLC

V

(3)

, VO = GND –60 –120 — mA

VIN = VIH or VIL IOL = 48mA MIL.

NOTES: 2614 tbl 05

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

5. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA
for military. Derate I

CC = 5.0V, +25°C ambient and maximum loading.

OL for number of outputs exceeding 8 turned on simultaneously.

I = GND — — –15

(4)

OH = –15mA COM’L. 2.4 4.3 —

I

OL = 64mA COM’L.

I

(5)

— 0.3 0.55

(5)

— 0.3 0.55

(2)

Max. Unit

VCC —

(4)

(4)

(4)

(4)

(4)

µA

µA

7.17 3

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC – 0.2V

(3)

(1)

Min. Typ.

— 0.5 2.0 mA

Symbol Parameter Test Conditions

CC Quiescent Power VCC = Max. — 0.2 1.5 mA

I

Supply Current V

IN ≥ VHC; VIN ≤ VLC

∆ICC Quiescent Power Supply VCC = Max., VIN = 3.4V

Current TTL Inputs HIGH

I

CCD Dynamic Power Supply Current

(4)

VCC = Max., Outputs Open VIN ≥ VHC — 0.15 0.25 mA/

CEAB

and

OEAB

CEBA

= V

= GND V

CC

IN ≤ VLC MHz

One Input Toggling
50% Duty Cycle

I

C Total Power Supply Current

(6)

VCC = Max., Outputs Open VIN ≥ VHC — 1.7 4.0 mA
f

CP = 10MHz (

LEAB

)VIN ≤ VLC

50% Duty Cycle (FCT)

CEAB

and

OEAB

= GND

CEBA

= V

CC

One Bit Toggling VIN = 3.4V — 2.2 6.0
at f

i = 5MHz VIN = GND

50% Duty Cycle
V

CC = Max., Outputs Open VIN ≥ VHC — 7.0 12.8

fCP = 10MHz (

LEAB

)VIN ≤ VLC

50% Duty Cycle (FCT)

CEAB

and

OEAB

= GND

CEBA

= V

CC

Eight Bits Toggling VIN = 3.4V — 9.2 21.8
at fi = 5MHz VIN = GND
50% Duty Cycle

(2)

Max. Unit

(5)

(5)

NOTES: 2614 tbl 06

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Per TTL driven input (V

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the I

C = IQUIESCENT +IINPUTS + IDYNAMIC

6. I
IC = ICC + ∆ICC DHNT + ICCD(fCP/2 + fiNi)

CC = Quiescent Current

I

CC = Power Supply Current for a TTL High Input (VIN = 3.4V)

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

f

i = Input Frequency

f

i = Number of Inputs at fi

N
All currents are in milliamps and all frequencies are in megahertz.

CC = 5.0V, +25°C ambient.

IN = 3.4V); all other inputs at VCC or GND.

CC formula. These limits are guaranteed but not tested.

7.17 4

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT54/74FCT543 IDT54/74FCT543A IDT54/74FCT543C

Com’l. Mil. Com’l. Mil. Com’l. Mil.

(1)

(2)

Min.

Symbol Parameter Condition

t

PLH Propagation Delay CL = 50pF 2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns

t

PHL Transparent Mode RL = 500Ω

n to Bn or Bn to An

A

Max. Min.

tPLH Propagation Delay 2.5 12.5 2.5 14.0 2.5 8.0 2.5 9.0 2.5 7.0 2.5 8.0 ns
t

PHL

LEBA

to An,

LEAB

to Bn

tPZH Output Enable Time 2.0 12.0 2.0 14.0 2.0 9.0 2.0 10.0 2.0 8.0 2.0 9.0 ns
t

PZL

OEBA
CEBA

or
or

OEAB
CEAB

to An or Bn

to An or Bn

tPHZ Output Disable Time 2.0 9.0 2.0 13.0 2.0 7.5 2.0 8.5 2.0 6.5 2.0 7.5 ns
t

PLZ

OEBA
CEBA

or
or

OEAB
CEAB

to An or Bn

to An or Bn

tSU Set-up Time, HIGH or LOW 3.0 — 3.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

A

n or Bn to

H Hold Time, HIGH or LOW 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns

t

A

n or Bn to

W

t

LEBA

or

LEBA

or

LEAB

LEBA

or

LEAB

LEAB

Pulse Width 5.0 — 5.0 — 5.0 — 5.0 — 5.0 — 5.0 — ns

LOW

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Min.

(2)

Max. Unit

NOTES: 2513 tbl 07

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

7.17 5

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

VCC

Pulse

Generator

VIN

D.U.T.

RT

VOUT

50pF

CL

7.0V

500Ω

500Ω

SWITCH POSITION

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

DEFINITIONS: 2614 tbl 08

CL = Load capacitance: includes jig and probe capacitance.

T = Termination resistance: should be equal to ZOUT of the Pulse

R

Generator.

SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLOCK ENABLE

CLEAR

ETC.

t

tSU

SU

t

REM

t

t

H

H

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

3V

1.5V
0V

LOW-HIGH-LOW

HIGH-LOW-HIGH

PULSE

PULSE

1.5V

t

W

1.5V

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

t

t

PLH

PLH

t

t

PHL

PHL

3V

1.5V
0V

V

OH

1.5V
V

OL

3V

1.5V
0V

ENABLE AND DISABLE TIMESPROPAGATION DELAY

ENABLE DISABLE

3V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

t

PZL

SWITCH
CLOSED

t

PZH

SWITCH
OPEN

3.5V

1.5V

1.5V
0V

t

PHZ

t

PLZ

NOTES 2614 drw 05

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
t

R ≤ 2.5ns.

1.5V
0V

3.5V

0.3V

V

OL

V

OH

0.3V
0V

O ≤ 50Ω; tF ≤ 2.5ns;

7.17 6

IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

XXIDT FCT

Temperature

Range

XXXX

Device

Type

X

PackageXProcess

Blank
B

P
D
L
SO
E

543
543A
543C

54
74

Commercial
MIL-STD-883, Class B

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK

Octal Registered Transceiver
Fast Octal Registered Transceiver
Super Fast Octal Registered Transceiver

-55°C to +125°C
0

° to +70°C

2614 drw 04

7.17 7