Datasheet IDT74FCT574P, IDT74FCT574LB, IDT74FCT574L, IDT74FCT574EB, IDT74FCT574DB Datasheet (Integrated Device Technology)
...
Integrated Device Technology, Inc.
FEATURES:
• IDT54/74FCT374/534/574 equivalent to FAST speed
and drive
• IDT54/74FCT374A/534A/574A up to 30% faster than
FAST
• IDT54/74FCT374C/534C/574C up to 50% faster than
FAST
•I
OL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Edge triggered master/slave, D-type flip-flops
• Buffered common clock and buffered common threestate control
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
DESCRIPTION:
The IDT54/74FCT374/A/C, IDT54/74FCT534/A/C and
IDT54/74FCT574/A/C are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist
of eight D-type flip-flops with a buffered common clock and
buffered 3-state output control. When the output enable (OE)
is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements
of the D inputs is transferred to the O outputs on the LOW-toHIGH transition of the clock input.
The IDT54/74FCT374/A/C and IDT54/74FCT574/A/ C have
non-inverting outputs with respect to the data at the D inputs.
The IDT54/74FCT534/A/C have inverting outputs.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT374 AND IDT54/74FCT574
D0
O0
D1
O1
D2
O2
D3
O3
D4
O4
D5
O5
D6
O6
D7
O7
CP
OE
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT534
D
0
O
0
D
1
O
1
D
2
O
2
D
3
O
3
D
4
O
4
D
5
O
5
D
6
O
6
D
7
O
7
CP
OE
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
2603 cnv* 01
2603 cnv* 02
IDT54/74FCT374/A/C
IDT54/74FCT534/A/C
IDT54/74FCT574/A/C
FAST CMOS OCTAL D
REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992
1992 Integrated Device Technology, Inc. 7.13 DSC-4622/2
1
7.13 2
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
7
D
7
D
6
O
6
O
5
D
4
CP
D
5
O
4
V
CC
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
&
E20-1
IDT54/74FCT534
2603 cnv* 03 2603 cnv* 04
INDEX
D
1
O
1
O
2
D
2
D
3
D
7
D
6
O
6
O
5
D
5
O
0
D
0
OE
V
CC
O
7
O
3
GND
CP
O
4
D
4
LCC
TOP VIEW
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
9 10111213
L20-2
2603 cnv* 05 2603 cnv* 06
2603 cnv* 07 2603 cnv* 08
PIN CONFIGURATIONS
IDT54/74FCT374
IDT54/74FCT574
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
O
0
O
1
O
2
O
3
O
4
O
6
CP
O
5
O
7
V
CC
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
&
E20-1
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
O
7
D
7
D
6
O
6
O
5
D
4
CP
D
5
O
4
V
CC
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
&
E20-1
INDEX
D
2
D
3
D
4
D
5
D
6
O
1
O
2
O
3
O
4
O
5
D0
D1
OE
V
CC
O0
D7
GND
CP
O
7
O6
LCC
TOP VIEW
32 21
1
4
5
6
7
8
1
1
1
1
1
91111
L20-2
INDEX
D1 D7
O0
D0
OE
V
CC
O7
GND
LCC
TOP VIEW
D
6
O6
O5
D5
O1
O2
D2
D3
O4
D4
O3
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
9 10111213
L20-2
CP
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.13 3
PIN DESCRIPTION
2603 tbl 06
FUNCTION TABLE
(1)
NOTE: 2603 tbl 05
1. H = HIGH Voltage Level Z = High Impedance
L = LOW Voltage Level NC = No Change
X = Don’t Care
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES: 2603 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may
exceed V
CC by +0.5V unless otherwise noted.
2. Input and V
CC terminals only.
3. Outputs and I/O terminals only.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
C
IN
Input
Capacitance
VIN = 0V 6 10
pF
C
OUT
Output
Capacitance
V
OUT
= 0V 8 12
pF
NOTE: 2603 tbl 02
1. This parameter is measured at characterization but not tested.
Symbol Rating Commercial Military Unit
VTERM
(2)
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM
(3)
Terminal Voltage
with Respect to
GND
–0.5 to V
CC –0.5 to VCC V
TA Operating
Temperature
0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias
–55 to +125 –65 to +135 °C
TSTG Storage
Temperature
–55 to +125 –65 to +150 °C
PT Power Dissipation 0.5 0.5 W
IOUT DC Output
Current
120 120 mA
u
= LOW-to-HIGH transition
Pin Names Description
DN D flip-flop data inputs.
CP Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
ON 3-state outputs, (true).
O
N 3-state outputs, (inverted).
OE
Active LOW 3-state Output Enable input.
FCT534 FCT374/574
Inputs Outputs Internal Outputs Internal
Function
OE
OE
CP DN
O
O
N QN ON
Q
Q
N
Hi-Z H
H
L
H
X
X
Z
Z
NC
NC
Z
Z
NC
NC
Load Register L
L
H
H
u
u
u
u
L
H
L
H
H
L
Z
Z
L
H
L
H
L
H
Z
Z
H
L
H
L
7.13 4
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
NOTES: 2603 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC —— 5µA
VI = 2.7V — — 5
(4)
II L Input LOW Current VI = 0.5V — — –5
(4)
VI = GND — — –5
IOZH Off State (High Impedance) VCC = Max. VO = VCC ——10µA
Output Current VO = 2.7V — — 10
(4)
IOZL VO = 0.5V — — –10
(4)
VO = GND — — –10
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
(3)
, VO = GND –60 –120 — mA
VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µAVHC VCC —V
VCC = Min. IOH = –300µAVHC VCC —
VIN = VIH or VIL IOH = –12mA MIL. 2.4 4.3 —
IOH = –15mA COM'L. 2.4 4.3 —
VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300µA — GND VLC V
VCC = Min. IOL = 300µA — GND VLC
(4)
VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5
IOL = 48mA COM'L. — 0.3 0.5
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.13 5
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
NOTES: 2603 tbl 04
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC = 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC formula. These limits are guaranteed but not tested.
6. I
C = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
I
CC = Quiescent Current
∆I
CC = Power Supply Current for a TTL High Input (VIN = 3.4V)
D
H = Duty Cycle for TTL Inputs High
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
N
i = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max. Unit
ICC
Quiescent Power Supply Current VCC = Max.
V
IN ≥ VHC; V IN ≤ VLC
— 0.2 1.5 mA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
V
IN = 3.4V
(3)
— 0.5 2.0 mA
ICCD Dynamic Power Supply
Current
(4)
VCC = Max.
Outputs Open
OE
= GND
One Input Toggling
50% Duty Cycle
V
IN ≥ VHC
V
IN ≤ VLC
— 0.15 0.25 mA/
MHz
IC Total Power Supply Current
(6)
VCC = Max.
Outputs Open
f
CP = 10MHz
50% Duty Cycle
V
IN ≥ VHC
V
IN ≤ VLC
(FCT)
— 1.7 4.0 mA
OE
= GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
IN = 3.4V
V
IN = GND
— 2.2 6.0
VCC = Max.
Outputs Open
f
CP = 10MHz
50% Duty Cycle
V
IN ≥ VHC
V
IN ≤ VLC
(FCT)
— 4.0 7.8
(5)
OE
= GND
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle
V
IN = 3.4V
V
IN = GND
— 6.2 16.8
(5)
7.13 6
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT374/534/574 FCT374A/534A/574A FCT374C/534C/574C
Com'l. Mil. Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
tPLH
tPHL
Propagation Delay
CP to O
N
(3)
CL = 50pF
R
L = 500Ω
2.0 10.0 2.0 11.0 2.0 6.5 2.0 7.2 2.0 5.2 2.0 6.2 ns
tPZH
tPZL
Output Enable Time
1.5 12.5 1.5 14.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.2 ns
tPHZ
tPLZ
Output Disable Time
1.5 8.0 1.5 8.0 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.7 ns
tSU Set-up Time HIGH
or LOW, D
N to CP
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns
tH Hold Time HIGH
or LOW, D
N to CP
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
tW CP Pulse Width
HIGH or LOW
7.0 — 7.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns
NOTES: 2603 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. O
N for FCT374 and FCT574, ON for FCT534.
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.13 7
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMESPROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
Pulse
Generator
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
t
SU
t
H
t
REM
H
tSU
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF
500Ω
500Ω
7.0V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
V
OL
t
PLH
t
PHL
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
3V
1.5V
0V
t
PLH
t
PHL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
t
NOTES 2603 drw 15
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; Z
O ≤ 50Ω; tF ≤ 2.5ns;
t
R ≤ 2.5ns.
SWITCH POSITION
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
DEFINITIONS: 2603 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
R
T = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
7.13 8
IDT54/74FCT374/534/574/A/C
FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX
Temp. Range
XXXX
Device TypeXPackage
X
Process
Blank
B
P
D
SO
L
E
374
574
534
374A
574A
534A
374C
574C
534C
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-Inverting Octal D Register
Non-Inverting Octal D Register
Inverting Octal D Register
Fast Non-Inverting Octal D Register
Fast Non-Inverting Octal D Register
Fast Inverting Octal D Register
Super Fast Non-Inverting Octal D Register
Super Fast Non-Inverting Octal D Register
Super Fast Inverting Octal D Register
54
74
–55°C to +125°C
0°C to +70°C
FCT
2603 cnv* 14
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